IP Library Patent Application 18632236
Patent Application
App. No. 18/632,236

Dataflow Graph Performance Debugger And Design Rule Checker For CGRA

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Quick Facts
Patent No.
US None
App. No.
18/632,236
Abstract

A system comprising a tool for providing actionable insight for bring up and performance debug of performant dataflow graphs on CGRA. A system comprising a tool for providing hierarchical traceable graph transformation of dataflow graph and annotated with runtime information after the compilation and execution back onto higher levels of stack from hardware metrics. A system comprising a tool for system performance monitoring and tuning by composition of compile time and runtime information of a workload dataflow graph on CGRA.

Claims (14)

1 . A system, comprising:

a tool for providing actionable insight for bring up and performance debug of performant dataflow graphs on CGRA.

2 . A system, comprising:

a tool for providing hierarchical traceable graph transformation of dataflow graph and annotated with runtime information after the compilation and execution back onto higher levels of stack from hardware metrics.

3 . A system, comprising:

A tool for system performance monitoring and tuning by composition of compile time and runtime information of a workload dataflow graph on CGRA with one or more of the following steps:

a). intelligent combining of hardware performance counters and software compiler techniques for expert inspection and tuning of dataflow workflows via collated reports.

b). identifying and classifying possible performance bottlenecks based on ML classifiers based on the Decision Tree method. The classifiers will be trained by processed data and thresholds from compile artifact, benchmarking, and instrumentation reports of well-tuned models. This would take advantage of experienced performance engineers' efforts and provide another perspective for optimizing performance.

c). semi-automated recommendation engine to tune performance of dataflow workload by specific design rule checks to be met or violated and corresponding mitigation strategies; and provide iterated workflow for progressive performance tuning.

d). Identifying bottlenecks in workload using compile-time+runtime measurements for zero-down debug and bring up of performant dataflow workloads on CGRA.

4 . The system of claim 3 , further comprising semi-automated recommendation engine to tune performance of dataflow workload by specific design rule checks to be met or violated and corresponding mitigation strategies; and provide iterated workflow for progressive performance tuning.

5 . The system of claim 3 , further comprising performance debugger and design rule checker with capability to perform online analysis of workloads and provide automated recommendations as reports.

6 . The system of claim 3 , further comprising capability to plug in various analysis tools using compiler and runtime tools to publish the performance debugging reports.

7 . The system of claim 3 , further comprising performance debug tool work with actual hardware and compiler or simulated partial hardware from RTL and compiler.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2026
From: RAVNBORG, ANDERS
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 073734/0467 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2025
From: ANNAMALAI, MUTHIAH
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 072560/0926 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →