IP Library Granted Patent US 11,886,930
Granted Patent B2
US 11,886,930 · App. 17/522,672 · Granted Jan 30, 2024

Runtime execution of functions across reconfigurable processor

Inventors: Ram Sivaramakrishnan (San Jose, CA); Sumti Jairath (Santa Clara, CA); Emre Ali Burhan (Sunnyvale, CA); Manish K. Shah (Austin, TX); Raghu Prabhakar (San Jose, CA); Ravinder Kumar (Fremont, CA); Arnav Goel (San Jose, CA); Ranen Chatterjee (Fremont, CA); Gregory Frederick Grohoski (Bee Cave, TX); Kin Hing Leung (Cupertino, CA); Dawei Huang (San Diego, CA); Manoj Unnikrishnan (Saratoga, CA); Martin Russell Raumann (San Leandro, CA); Bandish B. Shah (San Francisco, CA)
Assignee: SambaNova Systems, Inc.
G06F9/5077G06F9/45558G06F9/5027G06F2009/4557
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Quick Facts
Patent No.
US 11,886,930
App. No.
17/522,672
Granted
Jan 30, 2024
Kind
B2
Abstract

The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.

Claims (27)

1. A data processing system, comprising:

a plurality of reconfigurable processors including a first reconfigurable processor operatively coupled to a first processing node and additional reconfigurable processors operatively coupled to a second processing node;

wherein the first reconfigurable processor and the additional reconfigurable processors are operatively coupled to different processing nodes;

a plurality of buffers, buffers in the plurality of buffers including first reconfigurable processor-to-additional reconfigurable processors buffers configured to receive data from the first reconfigurable processor and provide the data to the additional reconfigurable processors, and additional reconfigurable processors-to-first reconfigurable processor buffers configured to receive data from the additional reconfigurable processors and provide the data to the first reconfigurable processor;

runtime logic configured to load one or more configuration files for applications on the first reconfigurable processor for execution, the configuration files including a plurality of functions; and

the runtime logic configured to execute a first set of functions in the plurality of functions and data therefor on the first reconfigurable processor, and a second set of functions in the plurality of functions and data therefor on the additional reconfigurable processors,

wherein functions in the second set of functions and the data therefor are transmitted to the additional reconfigurable processors using one or more of the first reconfigurable processor-to-additional reconfigurable processors buffers,

wherein results of executing the functions and the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of the additional reconfigurable processors-to-first reconfigurable processor buffers, and

wherein the first reconfigurable processor-to-additional reconfigurable processors buffers operate in a memory of a first smart Network Interface Controller (SmartNIC) operatively coupled to the first processing node, and the additional reconfigurable processors-to-first reconfigurable processor buffers operate in a memory of a second SmartNIC operatively coupled to the second processing node.

2. A data processing system, comprising:

a plurality of reconfigurable processors including a first reconfigurable processor on a first processing node operatively coupled to a first host processor and additional reconfigurable processors on a second processing node operatively coupled to a second host processor, wherein the first processing node and the second processing node are operatively coupled by a network fabric;

a first Smart Network Interface Controller (SmartNIC) operatively coupled to the first reconfigurable processor, the first SmartNIC having a first plurality of buffers;

a second SmartNIC operatively coupled to the additional reconfigurable processors, the second SmartNIC having a second plurality of buffers; and

runtime logic configured to execute one or more configuration files that define applications and process application data for the applications using the first reconfigurable processor and the additional reconfigurable processors, and wherein execution of the configuration files and processing of the application data includes receiving configuration data in the configuration files and the application data from the first reconfigurable processor and providing the configuration data and the application data to at least one of the additional reconfigurable processors, and receiving the configuration data and the application data from at least one of the additional reconfigurable processors and providing the configuration data and the application data to the first reconfigurable processor;

wherein streaming of configuration data and the application data between the first reconfigurable processor and the additional reconfigurable processors is performed using one of the first plurality of buffers and the second plurality of buffers.

3. A data processing system, comprising:

a pool of reconfigurable dataflow resources including a plurality of processing nodes, respective processing nodes in the plurality of processing nodes operatively coupled to respective pluralities of reconfigurable processors and respective pluralities of buffers; and

a runtime processor operatively coupled to the pool of reconfigurable dataflow resources, the runtime processor including runtime logic configured to:

receive a set of configuration files for an application;

load and execute a first subset of configuration files in the set of configuration files and association application data on a first reconfigurable processor operatively coupled to a first processing node in the respective processing nodes;

load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor operatively coupled to a second processing node in the respective processing nodes; and

use a first plurality of buffers operatively coupled to the first processing node, and a second plurality of buffers operatively coupled to the second processing node to stream data between the first reconfigurable processor and the second reconfigurable processor to load and execute the first subset of configuration files and the second subset of configuration files;

wherein a network fabric operatively couples the first processing node and the second processing node, and streams the data between the first plurality of buffers and the second plurality of buffers; and

wherein the first plurality of buffers operates in a memory of a first smart Network Interface Controller (SmartNIC) operatively coupled to the first processing node, and the second plurality of buffers operates in a memory of a second SmartNIC operatively coupled to the second processing node.

4. The data processing system of claim 3 , wherein the runtime logic is further configured to:

load and execute a third subset of configuration files in the set of configuration files and associated application data on a third reconfigurable processor operatively coupled to a third processing node in the respective processing nodes; load and execute a fourth subset of configuration files in the set of configuration files and associated application data on a fourth reconfigurable processor operatively coupled to a fourth processing node in the respective processing nodes; and

use a third plurality of buffers operatively coupled to the third processing node, and a fourth plurality of buffers operatively coupled to the fourth processing node to stream data between the third reconfigurable processor and the fourth reconfigurable processor to load and execute the third subset of configuration files and the fourth subset of configuration files.

Assignments (2)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2021
From: SIVARAMAKRISHNAN, RAM; JAIRATH, SUMTI; BURHAN, EMRE ALI; SHAH, MANISH K.; PRABHAKAR, RAGHU; KUMAR, RAVINDER; GOEL, ARNAV; CHATTERJEE, RANEN; GROHOSKI, GREGORY FREDERICK; LEUNG, KIN HING; HUANG, DAWEI; UNNIKRISHNAN, MANOJ; RAUMANN, MARTIN RUSSELL; SHAH, BANDISH B.
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 058066/0195 →
Continuity (2)
Continuation 17127929 · Dec 18, 2020
Related Publication 20220197711A1 · Jun 23, 2022
Cited By (4)
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