Accelerator automation framework for heterogeneous computing in datacenters

1. A method for designing an information processing system comprising the steps of:

partitioning a design space of possible modifications to a source code into a plurality of independent partitions based on a defined set of rules;

assigning a unique processing core to each partition;

generating a plurality of starting points for each partition, wherein each starting point is associated with a machine learning algorithm; and

determining a set of feasible designs associated with the information processing system;

wherein the plurality of starting points include a performance-driven seed and an area-driven seed; and

wherein the design space comprises a range of values for buffer width, a range of values for loop tiling, a range of values for loop parallelization, and whether or not loop pipelining is enabled.

2. The method of claim 1 , wherein the design space is partitioned based on loop hierarchy associated with the source code.

3. The method of claim 1 , wherein the design space is partitioned based on an outermost kernel loop associated with the source code.

4. The method of claim 1 , wherein the design space is partitioned according to a machine learning model trained to associated design points of the design space to a partition of the plurality of independent partitions according to similarity in at least one of resource utilization and latency.

5. The method of claim 1 , wherein a set of feasible designs is determined using an iterative searching engine.

6. The method of claim 1 , further comprising terminating a process to determine the set of feasible designs based on a predetermined stopping condition.

7. The method of claim 6 , wherein the stopping condition is determined by computing a Shannon entropy associated with the design space.

8. The method of claim 1 , wherein the performance-driven seed is one in which pipelining is enabled for all loops of the source code.

9. The method of claim 1 , wherein the performance-driven seed is one in which parallelization for each loop of the source code is set to a predefined maximum parallelization value.

10. The method of claim 9 , wherein the performance-driven seed is one in which a buffer width is set to a predefined maximum buffer width.

11. The method of claim 10 , wherein the area-driven seed includes all loops of the source code performed sequentially and the buffer width set to a minimum bit width.

12. A system comprising:

one or more processing devices; and

one or more memory devices operably coupled to the one or more processing devices and storing executable code that, when executed by the one or more processing devices, causes the one or more processing devices to:

partition a design space of possible modifications to a source code into a plurality of independent partitions based on a defined set of rules;

assign a unique processing core to each partition;

generate a plurality of starting points for each partition, wherein each starting point is associated with a machine learning algorithm; and

determine a set of feasible designs for an information processing system based on the source code;

wherein the plurality of starting points for each partition include a performance-driven seed and an area-driven seed;

wherein the design space comprises a range of values for buffer width, a range of values for loop tiling, a range of values for loop parallelization, and whether or not loop pipelining is enabled;

wherein the performance-driven seed is one in which pipelining is enabled for all loops of the source code, parallelization for each loop of the source code is set to a predefined maximum parallelization value, and a buffer width is set to a predefined maximum buffer width.

13. The system of claim 12 , wherein the executable code, when executed by the one or more processing devices, further causes the one or more processing devices to partition the design space based on loop hierarchy associated with the source code.

14. The system of claim 12 , wherein the executable code, when executed by the one or more processing devices, further causes the one or more processing devices to partition the design space based on an outermost kernel loop associated with the source code.

15. The system of claim 12 , wherein the executable code, when executed by the one or more processing devices, further causes the one or more processing devices to partition the design space according to a machine learning model trained to associated design points of the design space to a partition of the plurality of independent partitions according to similarity in at least one of resource utilization and latency.

16. The system of claim 12 , wherein the executable code, when executed by the one or more processing devices, further causes the one or more processing devices to determine the set of feasible designs using an iterative searching engine.

17. The system of claim 12 , wherein the area-driven seed includes all loops of the source code performed sequentially and the buffer width set to a minimum bit width.

18. A non-transitory computer-readable medium storing executable code that, when executed by one or more processing devices, causes the one or more processing devices to:

partition a design space of possible modifications to a source code into a plurality of independent partitions based on a defined set of rules;

assign a unique processing core to each partition;

generate a plurality of starting points for each partition, wherein each starting point is associated with a machine learning algorithm; and

determine a set of feasible designs for an information processing system based on the source code;

wherein the design space is partitioned based on a loop hierarchy associated with the source code, the loop hierarchy including a plurality of levels of nested loops.