Resistive random access memory cells integrated with shared-gate vertical field effect transistors
A two-transistor-two-resistor (2T2R) resistive random access memory (ReRAM) structure, and a method for forming the same includes two vertical field effect transistors (VFETs) formed on a substrate, each VFET includes an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape that extend horizontally beyond the channel region. A metal gate material is disposed on and around the channel region. A portion of the metal gate material is located between the two VFETs. A ReRAM stack is deposited within two openings adjacent to a side of each VFET that is opposing the portion of the metal gate material located between the two VFETs. A portion of the epitaxial region in direct contact with the ReRAM stack acts as a bottom electrode for the ReRAM structure.
1. A semiconductor device, comprising:
two vertical field effect transistors, each vertical field effect transistor comprising an epitaxial region located above a channel region and below a dielectric cap, the epitaxial region comprising two opposing protruding regions of triangular shape that extend horizontally beyond the channel region;
a metal gate material disposed on and around the channel region, wherein a portion of the metal gate material is located between the two vertical field effect transistors;
an interlevel dielectric layer above the metal gate material; and
two resistive random access memory structures, each resistive random access memory is adjacent to a side of a vertical field effect transistor of the two vertical field effect transistors that is opposing the portion of the metal gate material located between the two vertical field effect transistors, wherein each of the resistive random access memory structures comprises an oxide layer located directly above the epitaxial region, a top electrode layer directly above the oxide layer and a metal fill above the top electrode layer, wherein the epitaxial region acts as a bottom electrode for the resistive random access memory structure.
2. The semiconductor device of claim 1 , wherein the two vertical field effect transistor further comprises:
a doped source on a substrate, the channel region extending from the doped source.
3. The semiconductor device of claim 2 , further comprises:
a counter-doped layer between the substrate and the doped source, wherein the doped source comprises a first dopant, and the counter-doped layer comprises a second dopant that is different than the first dopant.
4. The semiconductor device of claim 3 , further comprising:
a source/drain contact contacting the doped source.
5. The semiconductor device of claim 1 , further comprising:
a gate contact contacting the metal gate material.
6. The semiconductor device of claim 1 , further comprising:
a resistive random access memory contact contacting a top portion of the metal fill in each vertical field effect transistor.