IP Library › Granted Patent US 11,669,368
Granted Patent B2
US 11,669,368 · App. 16/723,358 · Granted Jun 6, 2023

Multi-tenant data protection in edge computing environments

Inventors: Kshitij Arun Doshi (Tempe, AZ); Ned M. Smith (Beaverton, OR); Francesc Guim Bernat (Barcelona, ES); Timothy Verrall (Pleasant Hill, CA)
Assignee: Intel Corporation
G06F9/5016G06F8/443G06F9/44594G06F9/505G06F9/5072G06F9/5077G06F9/544G06F11/3433G06F16/1865G06F21/602H04L9/008H04L9/0637H04L9/0822H04L9/0825H04L9/0866H04L41/0893H04L41/0896H04L41/142H04L41/145H04L41/5009H04L41/5025H04L41/5051H04L43/08H04L47/822H04L63/0407H04L63/0428H04L63/1408H04L63/20H04L67/1008H04L67/12H04L67/141G06F9/3836G06F9/45533G06F9/4881G06F9/5038G06F11/1004G06F12/1408G06F16/2322G06F2209/509G16Y40/10H04L9/3297H04L67/10
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Quick Facts
Patent No.
US 11,669,368
App. No.
16/723,358
Filed
Dec 20, 2019
Granted
Jun 6, 2023
Kind
B2
Art Unit
2195
USPC
718/104
Abstract

In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.

Claims (63)

1. A system comprising:

memory; and

processing circuitry coupled to the memory, the processing circuitry configured to:

obtain a workflow execution plan, the workflow execution plan including workload metadata, the workload metadata defining a plurality of workloads associated with a plurality of edge service instances, the plurality of edge service instances executing on one or more edge computing devices within an edge computing system;

translate the workload metadata using a translation function to obtain workload configuration information for the plurality of workloads, the workload configuration information identifying a plurality of memory access configurations and service authorizations, the plurality of memory access configurations specifying a plurality of memory address ranges associated with access to the memory, and the service authorizations specifying at least one edge service instance of the plurality of edge service instances authorized to access one or more of the plurality of memory access configurations;

partition the memory into a plurality of shared memory regions associated with the plurality of memory address ranges using the plurality of memory access configurations, the plurality of shared memory regions of the memory configured for shared access among the plurality of edge service instances based at least on a mapping between the plurality of memory address ranges and identification information of the plurality of edge service instances; and

process a memory access request for accessing at least one of the plurality of shared memory regions based on the service authorizations, the memory access request received from an edge service instance of the plurality of edge service instances.

2. The system of claim 1 , wherein the processing circuitry is further configured to:

translate the workload metadata using the translation function to obtain a plurality of functions scheduled for execution on the one or more edge computing devices.

3. The system of claim 2 , wherein the plurality of functions includes one or more of the following:

named function networking (NFN) functions; and

Function-as-a-Service (FaaS) functions.

4. The system of claim 2 , wherein the plurality of functions includes a homomorphic function, and the processing circuitry is further configured to:

register a function identification and a function bitstream of the homomorphic function with a shared protected memory region of the plurality of shared memory regions.

5. The system of claim 4 , wherein the plurality of memory access configurations specifies:

a memory address range of the plurality of memory address ranges, the memory address range associated with the shared protected memory region, the memory address range storing encrypted data;

device identification information of respective devices of the one or more edge computing devices authorized to access the homomorphic function; and

wherein the service authorizations identify a subset of the plurality of edge service instances authorized to access the memory address range associated with the shared protected memory region.

6. The system of claim 5 , wherein the encrypted data stored in the memory address range associated with the shared protected memory region is protected via homomorphic encryption using the function bitstream of the homomorphic function.

7. The system of claim 6 , wherein the memory access request identifies an edge service instance of the plurality of edge service instances requesting the memory access and an edge computing device of the one or more edge computing devices executing the requesting edge service instance.

8. The system of claim 7 , wherein the processing circuitry is further configured to:

perform one or more data transformations on the encrypted data to process the memory access request, when the device identification information identifies the edge computing device executing the requesting edge service instance.

9. The system of claim 8 , wherein the processing circuitry is further configured to:

offload performing of the one or more data transformations on the encrypted data to at least one edge computing device of the one or more edge computing devices authorized to access the homomorphic function.

10. The system of claim 1 , wherein the plurality of memory access configurations specifies:

a memory address range of the plurality of memory address ranges, the memory address range associated with a protected memory region of the plurality of shared memory regions, wherein a trusted execution environment (TEE) of the edge computing device is configured using the protected memory region.

11. The system of claim 1 , wherein the plurality of memory access configurations includes a plurality of secure keys for accessing respective memory regions of the plurality of shared memory regions.

12. The system of claim 1 , wherein the processing circuitry is further configured to:

configure a virtual memory space mapped to at least one of the plurality of shared memory regions and to a second virtual memory space in an edge computing device of the one or more edge computing devices, the edge computing device authorized to access the at least one of the plurality of shared memory regions.

13. The system of claim 12 , wherein the virtual memory space is mapped to the second virtual memory space in the edge computing device using a distributed lock manager (DLM) service.

14. The system of claim 13 , wherein the processing circuitry is further configured to:

update data stored in the at least one of the plurality of shared memory regions based on the memory access request; and

map the updated data stored in the at least one of the plurality of shared memory regions to the virtual memory space and to the second virtual memory space in the edge computing device via the DLM service.

15. The system of claim 1 , wherein the edge computing system is an Edge-as-a-Service (EaaS) system, and wherein the one or more edge computing device is an EaaS microservice node.

16. The system of claim 1 , wherein the mapping between the plurality of memory address ranges and the identification information of the plurality of edge service instances is included in a mapping table.

17. At least one non-transitory machine-readable storage medium comprising instructions, wherein the instructions, when executed by a processing circuitry of an edge computing device operable in an edge computing system, cause the processing circuitry to perform operations that:

obtain a workflow execution plan, the workflow execution plan including workload metadata, the workload metadata defining a plurality of workloads associated with a plurality of edge service instances, the plurality of edge service instances executing on one or more edge computing devices within an edge computing system;

translate the workload metadata using a translation function to obtain workload configuration information for the plurality of workloads, the workload configuration information identifying a plurality of memory access configurations and service authorizations, the plurality of memory access configurations specifying a plurality of memory address ranges associated with access to the memory, and the service authorizations specifying at least one edge service instance of the plurality of edge service instances authorized to access one or more of the plurality of memory access configurations;

partition memory of the edge computing device into a plurality of shared memory regions associated with the plurality of memory address ranges using the plurality of memory access configurations, the plurality of shared memory regions of the memory configured for shared access among the plurality of edge service instances based at least on a mapping between the plurality of memory address ranges and identification information of the plurality of edge service instances; and

process a memory access request for accessing at least one of the plurality of shared memory regions based on the service authorizations, the memory access request received from an edge service instance of the plurality of edge service instances.

18. The machine-readable storage medium of claim 17 , wherein the plurality of memory access configurations specifies:

a memory address range of the plurality of memory address ranges, the memory address range associated with a shared memory region of the plurality of shared memory regions; and

device identification information of at least one edge computing device of the one or more edge computing devices authorized to share data stored in the shared memory region.

19. The machine-readable storage medium of claim 18 , wherein the service authorizations include process address space identifiers (PASIDs) identifying a subset of the plurality of edge service instances authorized to access the memory address range associated with the shared memory region.

20. The machine-readable storage medium of claim 19 , wherein the memory access request includes a PASID of an edge service instance of the plurality of edge service instances requesting the memory access and identifies at least a second edge computing device of the one or more edge computing devices executing the requesting edge service instance.

21. The machine-readable storage medium of claim 20 , wherein the instructions further cause the processing circuitry to perform operations that:

perform a memory read or a memory write operation on the data stored in the shared memory region to process the memory access request when the device identification information identifies the second edge computing device executing the requesting edge service instance and the PASIDs within the service authorizations include the PASID within the memory access request.

22. A method performed by an edge computing device operable in an edge computing system, comprising:

obtaining a workflow execution plan, the workflow execution plan including workload metadata, the workload metadata defining a plurality of workloads associated with a plurality of edge service instances, the plurality of edge service instances executing on one or more edge computing devices within an edge computing system;

translating the workload metadata using a translation function to obtain workload configuration information for the plurality of workloads, the workload configuration information identifying a plurality of memory access configurations and service authorizations, the plurality of memory access configurations specifying a plurality of memory address ranges associated with access to the memory, and the service authorizations specifying at least one edge service instance of the plurality of edge service instances authorized to access one or more of the plurality of memory access configurations;

partitioning memory of the edge computing device into a plurality of shared memory regions associated with the plurality of memory address ranges using the plurality of memory access configurations, the plurality of shared memory regions of the memory configured for shared access among the plurality of edge service instances based at least on a mapping between the plurality of memory address ranges and identification information of the plurality of edge service instances; and

processing a memory access request for accessing at least one of the plurality of shared memory regions based on the service authorizations, the memory access request received from an edge service instance of the plurality of edge service instances.

23. The method of claim 22 , further comprising:

translating the workload metadata to obtain a plurality of functions scheduled for execution on the one or more edge computing devices.

24. The method of claim 23 , wherein the plurality of functions includes a homomorphic function, and the method further comprises:

registering a function identification and a function bitstream of the homomorphic function with a shared protected memory region of the plurality of shared memory regions.

25. The method of claim 24 , wherein the plurality of memory access configurations specifies:

a memory address range of the plurality of memory address ranges, the memory address range associated with the shared protected memory region, the memory range storing encrypted data;

device identification information of respective devices of the one or more edge computing devices authorized to access the homomorphic function; and

wherein the service authorizations identify a subset of the plurality of edge service instances authorized to access the memory address range associated with the shared protected memory region.

26. The method of claim 22 , wherein the plurality of memory access configurations specifies:

a memory address range of the plurality of memory address ranges, the memory address range associated with a shared memory region of the plurality of shared memory regions; and

device identification information of at least one edge computing device of the one or more edge computing devices authorized to share data stored in the shared memory region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2020
From: DOSHI, KSHITIJ ARUN; SMITH, NED M; GUIM BERNAT, FRANCESC; VERRALL, TIMOTHY
To: INTEL CORPORATION
Reel/Frame 052544/0538 →
Continuity (3)
Provisional Application 62939303 · Nov 22, 2019
Provisional Application 62907597 · Sep 28, 2019
Related Publication 20200134207A1 · Apr 30, 2020
Cited By (4)
US 12,192,081 US 12,206,552 US 12,373,595 US 12,386,686