IP Library › Granted Patent US 11,158,106
Granted Patent B2
US 11,158,106 · App. 16/723,969 · Granted Oct 26, 2021

VRS rate feedback

Inventors: Skyler Jonathon Saleh (La Jolla, CA); Vineet Goel (La Jolla, CA); Pazhani Pillai (Boxborough, MA); Ruijin Wu (La Jolla, CA); Christopher J. Brennan (Boxborough, MA); Andrew S. Pomianowski (Bellevue, WA)
Assignee: Advanced Micro Devices, Inc.
G06T15/005G06T1/20G06T1/60G06T2210/52
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Quick Facts
Patent No.
US 11,158,106
App. No.
16/723,969
Granted
Oct 26, 2021
Kind
B2
Abstract

Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

Claims (67)

1. A method for performing shader operations, the method comprising:

performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data;

updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data; and

writing to a VRS rate feedback buffer based on the updated VRS data.

2. The method of claim 1 , wherein:

the VRS rate feedback buffer includes indications for each tile of the one or more tiles, wherein the indications indicate either a shading rate for a tile based on the pixel shader variable rate shading data or that the tile includes a triangle edge.

3. The method of claim 1 , further comprising:

performing a post-processing task utilizing the VRS rate feedback buffer to reduce a rate at which the post-processing task occurs for at least one tile.

4. The method of claim 3 , wherein utilizing the VRS rate feedback buffer to reduce a rate at which the post-processing task occurs for at least one tile comprises:

if the VRS rate feedback buffer does not indicate that the at least one tile includes a triangle edge, then performing the post-processing task at a shading rate referred to in the VRS rate feedback buffer; and

if the VRS rate feedback buffer does indicate that the at least one tile includes a triangle edge, then performing the post-processing task at a shading rate of a render target.

5. The method of claim 1 , wherein updating the pixel shader VRS data for a tile of the one or more tiles includes:

determining that a coarse depth test indicates that the tile is partially covered by a triangle; and

in response to the determining, modifying a VRS data for the tile to indicate that the tile includes a triangle edge.

6. The method of claim 1 , wherein updating the pixel shader VRS data for a tile of the one or more tiles includes:

determining that a coarse depth test indicates that the tile is fully covered by a triangle; and

in response to the determining, setting, as a shading rate for the tile in updated VRS data, a shading rate of the tile in the pixel shader variable rate shading data.

7. The method of claim 1 , wherein:

the VRS data includes an indication that a tile of the one or more tiles is fully covered; and

updating the pixel shader VRS data for the tile of the one or more tiles includes:

determining that a pixel shader stage has modified coverage for at least one fragment in the tile to indicate that the at least one fragment is not covered; and

in response to the determining, modifying the pixel shader VRS data to indicate that the tile includes a triangle edge.

8. The method of claim 1 , wherein:

the VRS data includes an indication that a tile of the one or more tiles is fully covered; and

updating the pixel shader VRS data for the tile of the one or more tiles includes:

determining that a pixel shader stage has not modified coverage for any fragment in the tile to indicate that the at least one fragment is not covered; and

in response to the determining, setting, as a shading rate for the tile in updated VRS data, a shading rate of the tile in the pixel shader variable rate shading data.

9. The method of claim 1 , wherein writing the VRS rate feedback buffer based on the updated VRS data comprises:

writing first updated VRS data for a tile having a first depth to the VRS rate feedback buffer; and

in response to determining that second updated VRS data includes data that occludes the first updated VRS data, overwriting the first updated VRS data with the second updated VRS data in the VRS rate feedback buffer.

10. A graphics processing pipeline, comprising:

pixel shader stage circuitry configured to perform pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data; and

output merger stage circuitry configured to:

update the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data; and

write to a VRS rate feedback buffer based on the updated VRS data.

11. The graphics processing pipeline of claim 10 , wherein:

the VRS rate feedback buffer includes indications for each tile of the one or more tiles, wherein the indications indicate either a shading rate for a tile based on the pixel shader variable rate shading data or that the tile includes a triangle edge.

12. The graphics processing pipeline of claim 10 , further comprising post-processing circuitry configured to:

perform a post-processing task utilizing the VRS rate feedback buffer to reduce a rate at which the post-processing task occurs for at least one tile.

13. The graphics processing pipeline of claim 12 , wherein utilizing the VRS rate feedback buffer to reduce a rate at which the post-processing task occurs for at least one tile comprises:

if the VRS rate feedback buffer does not indicate that the at least one tile includes a triangle edge, then performing the post-processing task at a shading rate referred to in the VRS rate feedback buffer; and

if the VRS rate feedback buffer does indicate that the at least one tile includes a triangle edge, then performing the post-processing task at a shading rate of a render target.

14. The graphics processing pipeline of claim 10 , wherein updating the pixel shader VRS data for a tile of the one or more tiles includes:

determining that a coarse depth test indicates that the tile is partially covered by a triangle; and

in response to the determining, modifying a VRS data for the tile to indicate that the tile includes a triangle edge.

15. The graphics processing pipeline of claim 10 , wherein updating the pixel shader VRS data for a tile of the one or more tiles includes:

determining that a coarse depth test indicates that the tile is fully covered by a triangle; and

in response to the determining, setting, as a shading rate for the tile in updated VRS data, a shading rate of the tile in the pixel shader variable rate shading data.

16. The graphics processing pipeline of claim 10 , wherein:

the VRS data includes an indication that a tile of the one or more tiles is fully covered; and

updating the pixel shader VRS data for the tile of the one or more tiles includes:

determining that a pixel shader stage has modified coverage for at least one fragment in the tile to indicate that the at least one fragment is not covered; and

in response to the determining, modifying the pixel shader VRS data to indicate that the tile includes a triangle edge.

17. The graphics processing pipeline of claim 10 , wherein:

the VRS data includes an indication that a tile of the one or more tiles is fully covered; and

updating the pixel shader VRS data for the tile of the one or more tiles includes:

determining that a pixel shader stage has not modified coverage for any fragment in the tile to indicate that the at least one fragment is not covered; and

in response to the determining, setting, as a shading rate for the tile in updated VRS data, a shading rate of the tile in the pixel shader variable rate shading data.

18. The graphics processing pipeline of claim 10 , wherein writing the VRS rate feedback buffer based on the updated VRS data comprises:

writing first updated VRS data for a tile having a first depth to the VRS rate feedback buffer; and

in response to determining that second updated VRS data includes data that occludes the first updated VRS data, overwriting the first updated VRS data with the second updated VRS data in the VRS rate feedback buffer.

19. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform shader operations, the shading operations comprising:

performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data;

updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data; and

writing to a VRS rate feedback buffer based on the updated VRS data.

20. The non-transitory computer-readable medium of claim 19 , wherein:

the VRS rate feedback buffer includes indications for each tile of the one or more tiles, wherein the indications indicate either a shading rate for a tile based on the pixel shader variable rate shading data or that the tile includes a triangle edge.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2020
From: SALEH, SKYLER JONATHON; GOEL, VINEET; PILLAI, PAZHANI; WU, RUIJIN; BRENNAN, CHRISTOPHER J.; POMIANOWSKI, ANDREW S.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 051465/0661 →
Continuity (1)
Related Publication 20210192827A1 · Jun 24, 2021