Delay-locked loop, memory device, and method for operating delay-locked loop

1. A delay-locked loop circuit, comprising:

a delay line, including a plurality of delay units, for delaying an input signal to generate a first delay signal; and

a control unit receiving the input signal, an access start signal and an access end signal, the control unit configured for generating a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line to generate the first delay signal during a time interval between two read operations.

2. The delay-locked loop circuit of claim 1 , wherein the control unit transmits the control signal to the delay line after a number of clock cycles have occurred.

3. The delay-locked loop circuit of claim 2 , wherein the control unit further comprises a counter for counting the number of clock cycles.

4. The delay-locked loop circuit of claim 1 , wherein the control unit transmits the control signal to the delay line after a time period has elapsed.

5. The delay-locked loop circuit of claim 4 , wherein the control unit further comprises a timer for determining the time period.

6. The delay-locked loop circuit of claim 1 , further comprising a phase detector receiving the input signal and a feedback signal, the phase detector configured for selectively detecting phases of the input signal and the feedback signal to generate a phase detection result, wherein the phase detection result functions to control the delay line during the read operations, and the feedback signal is generated according to the first delay signal.

7. The delay-locked loop circuit of claim 6 , further comprising:

a clock tree configured for delaying the first delay signal to generate a second delay signal;

an off-chip device (OCD) receiving the second delay signal and an output data; and

a delay mimic receiving the first delay signal and generating the feedback signal, wherein a dummy delay in the feedback signal is used to match delays of the clock tree and the OCD.

8. A memory device, comprising:

a plurality of memory cells; and

a plurality of peripheral devices for reading data from and writing data to the memory cells, the peripheral devices comprising a delay-locked loop circuit comprising:

a delay line, including a plurality of delay units, the delay line configured for delaying an input signal to generate a first delay signal; and

a control unit receiving the input signal, an access start signal and an access end signal, the control unit configured for generating a control signal according to the input signal, the access start signal and the access end signal to control the delay line to generate the first delay signal during a time interval between two read operations.

9. The memory device of claim 8 , wherein the control unit transmits the control signal to the delay line after a number of clock cycles have occurred.

10. The memory device of claim 9 , wherein the control unit further comprises a counter for counting the number of clock cycles.

11. The memory device of claim 8 , wherein the control unit transmits the control signal to the delay line after a time period has elapsed.

12. The memory device of claim 11 , wherein the control unit further comprises a timer for determining the time period.

13. The memory device of claim 8 , further comprising a phase detector receiving the input signal and a feedback signal, the phase detector configured for selectively detecting phases of the input signal and the feedback signal to generate a phase detection result, wherein the phase detection result functions to control the delay line during the read operations, and the feedback signal is generated according to the first delay signal.

14. The memory device of claim 8 , further comprising:

a clock tree configured for delaying the first delay signal to generate a second delay signal;

an off-chip device (OCD) receiving the second delay signal and an output data; and

a delay mimic receiving the first delay signal and generating the feedback signal, wherein a dummy delay in the feedback signal is used to match delays of the clock tree and the OCD.

15. A method of operating a delay-locked loop circuit, comprising:

applying an input signal to a delay line including a plurality of delay units, and delaying the input signal with the delay line to generate a first delay signal; and

inputting the input signal, an access start signal and an access end signal to a control unit, and generating a control signal by the control unit according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line to generate the first delay signal during a time interval between read operations.

16. The method of claim 15 , further comprising counting a number of clock cycles between the access start signal and the access end signal by a counter, and generating the control signal after a predetermined number of clock cycles have been counted by the counter.

17. The method of claim 15 , further comprising determining a time period between the access start signal and the access end signal by a timer, and generating the control signal after a time segment has elapsed.

18. The method of claim 15 , further comprising:

inputting the input signal and a feedback signal to a phase detector, and selectively detecting phases of the input signal and the feedback signal by the phase detector to generate a phase detection result, wherein the phase detection result functions to control the delay line during the read operations, and the feedback signal is generated according to the first delay signal.