High performance fast Mux-D scan flip-flop
A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.
1. An apparatus comprising:
a primary latch comprising a first data path and a second data path, wherein the first data path comprises a scan path which is input into a memory circuitry of the primary latch, and wherein the second data path is a non-scan path which is input via a transmission gate coupled to the memory circuitry; and
a secondary latch coupled to the primary latch; and
circuitry to generate scan select based gated clocks derived from an input clock and provide the scan select based gated clocks to the primary latch, the circuitry comprising:
an inverter having an input coupled to an input clock, and an output;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal as input; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal as input.
2. The apparatus of claim 1 comprising:
a first inverter to receive an input data; and
a second inverter coupled in series with the first inverter, wherein the second inverter is coupled to the transmission gate.
3. The apparatus of claim 1 , wherein the memory circuitry comprises:
a first tri-statable inverter having an input coupled to the transmission gate; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable and the scan path, wherein an output of the second tri-statable inverter is coupled to the transmission gate.
4. The apparatus of claim 3 , wherein the transmission gate is a first transmission gate, wherein the secondary latch is coupled to the primary latch via an inverter, and wherein the secondary latch comprises a second transmission gate coupled to an output of the inverter.
5. The apparatus of claim 4 , wherein the memory circuitry is a first memory circuitry, wherein the secondary latch comprises a second memory circuitry coupled to the second transmission gate.
6. The apparatus of claim 4 , wherein the scan path comprises a third tri-statable inverter with an input coupled to a scan input and an output coupled to the input of the second tri-statable inverter.
7. The apparatus of claim 6 , wherein the scan select based gated clocks are to:
control the first transmission gate;
control the first and second tri-statable inverters of the memory circuitry; and
control the third tri-statable inverter of the scan path.
8. The apparatus of claim 1 , wherein a data input is directly received by the transmission gate without intervening buffers or inverters.
9. An apparatus comprising:
circuitry to generate scan select based gated clocks derived from an input clock; and
a vectored flip-flop circuitry to receive scan select based gated clocks from the circuitry, wherein a flip-flop of the vectored flip-flop circuitry comprises:
a primary latch comprising a first data path and a second data path, wherein the first data path comprises a scan path which is input into a memory circuitry of the primary latch, and wherein the second data path is a non-scan path which is input via a transmission gate coupled to the memory circuitry; and
a secondary latch coupled to the primary latch;
wherein the memory circuitry comprises:
a first tri-statable inverter having an input coupled to the transmission gate; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the transmission gate;
wherein the scan path comprises a third tri-statable inverter with an input coupled to a scan input and an output coupled to the input of the second tri-statable inverter; and
wherein the circuitry comprises:
an inverter having an input coupled to an input clock, and an output;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal as input; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal as input.
10. The apparatus of claim 9 , wherein the flip-flop of the vectored flip-flop circuitry comprises:
a first inverter to receive an input data; and
a second inverter coupled in series with the first inverter, wherein the second inverter is coupled to the transmission gate.
11. The apparatus of claim 10 , wherein the transmission gate is a first transmission gate, wherein the secondary latch is coupled to the master latch via an inverter, wherein the secondary latch comprises a second transmission gate coupled to an output of the inverter.
12. The apparatus of claim 11 , wherein the memory circuitry is a first memory circuitry, wherein the secondary latch comprises a second memory circuitry coupled to the second transmission gate.
13. The apparatus of claim 11 , wherein the scan select based gated clocks are to:
control the first transmission gate;
control the first and second tri-statable inverters of the memory circuitry; and
control the third tri-statable inverter of the scan path.
14. The apparatus of claim 9 , wherein a data input is directly received by the transmission gate without intervening buffers or inverters,
wherein the scan select based gated clocks are to:
control the first gate;
control the first and second tri-statable inverters of the memory circuitry; and
control the tri-statable inverter of the scan path.
15. A system comprising:
a memory;
a processor coupled to the memory, wherein the processor includes:
a critical timing path which includes a flip-flop comprising:
a primary latch comprising a first data path and a second data path, wherein the first data path comprises a scan path which is input into a memory circuitry of the primary latch, and wherein the second data path is a non-scan path which is input via a transmission gate coupled to the memory circuitry; and
a secondary latch coupled to the primary latch;
circuitry to generate scan select based gated clocks derived from an input clock and provide the scan select based gated clocks to the primary latch, the circuitry comprising:
an inverter having an input coupled to an input clock, and an output;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal as input; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal as input; and
a wireless interface to allow the processor to communicate with another device.
16. The system of claim 15 , wherein the processor further comprises:
a first inverter to receive an input data; and
a second inverter coupled in series with the first inverter, wherein the second inverter is coupled to the transmission gate.
17. The system of claim 15 , wherein the memory circuitry comprises:
a first tri-statable inverter having an input coupled to the transmission gate; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable and the scan path, wherein an output of the second tri-statable inverter is coupled to the transmission gate.
18. The apparatus of claim 17 , wherein the transmission gate is a first transmission gate, wherein the secondary latch is coupled to the primary latch via an inverter, and wherein the secondary latch comprises a second transmission gate coupled to an output of the inverter.
19. The apparatus of claim 18 , wherein the scan path comprises a third tri-statable inverter with an input coupled to a scan input and an output coupled to the input of the second tri-statable inverter.
20. The apparatus of claim 19 , wherein the scan select based gated clocks are to:
control the first transmission gate;
control the first and second tri-statable inverters of the memory circuitry; and
control the third tri-statable inverter of the scan path.