Coaxial via arrangement in probe card for automated test equipment
A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
1. A probe card for testing a semiconductor wafer, the probe card comprising:
a board comprising:
a first surface, a second surface separated from the first surface in a first direction, and an interior between the first surface and the second surface;
a plurality of pads on the first surface configured to be connected with a plurality of wafer pads on the semiconductor wafer via a plurality of probe pins contacting the plurality of pads;
at least one layer of conductors in the interior; and
a first via in the board, elongated in the first direction and in contact with a first pad of the plurality of pads;
a second via in the board, elongated in the first direction, and at least partially surrounding the first via,
wherein:
the second via comprises a perimeter facing the first via,
the first via is a signal via, and the second via is a ground via, and
the second via comprises a plurality of vias connected to a common ground plane in the board.
2. The probe card of claim 1 , wherein the board comprises a plurality of dielectric layers, and wherein the first via is a stack of a plurality of conductive fill material disposed within respective dielectric layers.
3. The probe card of claim 2 , wherein the board is a multiple layer organic (MLO) board.
4. A probe card for testing a semiconductor wafer, the probe card comprising:
a board comprising:
a first surface, a second surface separated from the first surface in a first direction, and an interior between the first surface and the second surface;
a plurality of pads on the first surface configured to be connected with a plurality of wafer pads on the semiconductor wafer via a plurality of probe pins contacting the plurality of pads;
at least one layer of conductors in the interior; and
a first via in the board, elongated in the first direction and in contact with a first pad of the plurality of pads;
a second via in the board, elongated in the first direction, and at least partially surrounding the first via,
wherein:
the second via comprises a perimeter facing the first via
the first via is a signal via, and the second via is a ground via, and
the second via comprises a plurality of trenches extending in a plane perpendicular to the first direction.
5. The probe card of claim 4 , wherein the perimeter is elongated along a second direction in parallel with the first surface and is longer than an extent of the first via along the second direction.
6. The probe card of claim 5 , wherein the second via has a trapezoidal shape at a cross-section along a plane perpendicular to the second direction.
7. The probe card of claim 4 , wherein the perimeter is shaped as a rectangle.
8. The probe card of claim 4 , wherein the perimeter is shaped as an arc.
9. The probe card of claim 4 , wherein the perimeter is shaped as a circle.
10. A probe card for testing a semiconductor wafer, the probe card comprising:
a board comprising:
a first surface, a second surface separated from the first surface in a first direction, and an interior between the first surface and the second surface;
a plurality of pads on the first surface configured to be connected with a plurality of wafer pads on the semiconductor wafer via a plurality of probe pins contacting the plurality of pads;
at least one layer of conductors in the interior; and
a first via in the board, elongated in the first direction and in contact with a first pad of the plurality of pads;
a second via in the board, elongated in the first direction, and at least partially surrounding the first via,
wherein:
the second via comprises a perimeter facing the first via, and
the first pad is disposed in a first plane, and the second via is in contact with a second pad disposed in a second plane different from the first plane.
11. The probe card of claim 10 , wherein the second pad at least partially surrounds the first pad.
12. The probe card of claim 10 , wherein the second pad comprises a circular opening that encloses the first pad.
13. The probe card of claim 10 , further comprising a third via connecting the second pad to a third pad, wherein the third pad is coplanar with the first pad.
14. The probe card of claim 10 , wherein second pad is a ground pad, and wherein the first pad is a signal pad.
15. The probe card of claim 10 , wherein the first via is in direct contact with a conductor in a third plane, the second via is in direct contact with a conductor in a fourth plane, wherein:
the second plane and the fourth plane are between the first and third planes.