Metallization in integrated circuit structures
Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.
1. An integrated circuit (IC) structure, comprising:
a first nanowire in a metal region; and
a second nanowire in the metal region;
wherein a distance between the first nanowire and the second nanowire is less than 5 nanometers, the metal region includes tungsten between the first nanowire and the second nanowire, the metal region includes a first portion between the first nanowire and the second nanowire, the metal region includes a second portion not between the first nanowire and the second nanowire, and a ratio of chlorine to fluorine in the first portion is less than a ratio of chlorine to fluorine in the second portion.
2. The IC structure of claim 1 , wherein an average grain size of the tungsten in a portion of the metal region is less than 8 nanometers.
3. The IC structure of claim 1 , wherein an average grain size of the tungsten in a portion of the metal region is less than 6 nanometers.
4. The IC structure of claim 1 , wherein the first nanowire includes silicon or germanium.
5. The IC structure of claim 1 , wherein the first nanowire has a thickness between 4 nanometers and 10 nanometers.
6. The IC structure of claim 1 , wherein the first nanowire has a width between 5 nanometers and 50 nanometers.
7. The IC structure of claim 1 , wherein the first nanowire, the second nanowire, and the metal region are part of a gate-all-around transistor.
8. The IC structure of claim 1 , wherein the metal region includes molybdenum.
9. An integrated circuit (IC) structure, comprising:
a first nanowire in a metal region; and
a second nanowire in the metal region, wherein the metal region includes a first portion between the first nanowire and the second nanowire, and the metal region includes a second portion not between the first nanowire and the second nanowire;
wherein a ratio of chlorine to fluorine in the first portion is less than a ratio of chlorine to fluorine in the second portion.
10. The IC structure of claim 9 , wherein the metal region includes tungsten.
11. The IC structure of claim 9 , wherein the first nanowire includes silicon or germanium.
12. The IC structure of claim 9 , further comprising:
a first portion of high-k material around the first nanowire in the metal region; and
a second portion of high-k material around the second nanowire in the metal region.
13. The IC structure of claim 12 , wherein the high-k material includes hafnium.
14. The IC structure of claim 9 , wherein the first nanowire, the second nanowire, and the metal region are part of a gate-all-around transistor.
15. The IC structure of claim 9 , wherein the metal region includes molybdenum.
16. An integrated circuit (IC) structure, comprising:
a first nanowire in a metal region; and
a second nanowire in the metal region
wherein the metal region includes tungsten, an average grain size of the tungsten in a portion of the metal region is less than 8 nanometers, the metal region includes a first portion between the first nanowire and the second nanowire, and the metal region includes a second portion not between the first nanowire and the second nanowire, and a ratio of chlorine to fluorine in the first portion is less than a ratio of chlorine to fluorine in the second portion.
17. The IC structure of claim 16 , wherein the average grain size of the tungsten in the portion of the metal region is less than 6 nanometers.
18. The IC structure of claim 16 , wherein the first nanowire includes silicon or germanium.
19. The IC structure of claim 16 , wherein the first nanowire has a thickness between 4 nanometers and 10 nanometers.
20. The IC structure of claim 16 , wherein the first nanowire, the second nanowire, and the metal region are part of a gate-all-around transistor.