Detection of a DMA (direct memory access) memory address violation when testing PCIE devices

1. A method for testing PCie devices, the method comprising:

enabling an input/output (I/O) memory management unit (IOMMU);

adding a peripheral component interconnect express (PCie) device;

creating by the IOMMU a domain, wherein the domain is a specified virtual memory address space for the device;

allocating by the IOMMU the domain to the device, wherein the domain defines access-allowed memory address spaces of virtual memory for the device;

mapping a physical memory address space to virtual address space, wherein the physical memory space is physical memory addresses for the device;

monitoring direct memory access (DMA) for accesses by the device to memory space that are outside of the domain; and

detecting a DMA memory address violation by the PCIe device.

2. The method of claim 1 , wherein monitoring is repeated until intentionally stopped.

3. The method of claim 1 , wherein the IOMMU includes the virtual memory address space and the physical memory address space.

4. The method of claim 2 , wherein the IOMMU further comprises an address mapping function.

5. The method of claim 4 , wherein the address mapping function maps a virtual address of a target device in the virtual memory address space to a physical address in the physical memory address space.

6. A non-transitory computer readable medium storing a kernel configuration module which, when executed by a processor of a computing device, tests PCie devices, the kernel configuration module comprising sets of instructions for:

enabling an input/output (I/O) memory management unit (IOMMU) of the computing device;

adding a peripheral component interconnect express (PCie) device;

creating by the IOMMU a domain, wherein the domain is a specified virtual memory address space for the device;

allocating by the IOMMU the domain to the device, wherein the domain defines access-allowed memory address spaces of virtual memory for the device;

mapping a physical memory address space to virtual address space, wherein the physical memory space is physical memory addresses for the device;

monitoring direct memory access (DMA) for accesses by the device to memory space that are outside of the domain; and

detecting a DMA memory address violation by a PCIe device.

7. The non-transitory computer readable medium of claim 6 , wherein allocating a memory space domain comprises allocating a memory address fence in a virtual memory address space of the IOMMU.

8. The non-transitory computer readable medium of claim 7 , wherein the IOMMU comprises the physical memory address space, an address mapping function, and the virtual memory address space.

9. The non-transitory computer readable medium of claim 8 , wherein adding a memory address for the PCie device comprises a set of instructions for mapping a virtual address of the PCie device in the virtual memory address space to a physical address in the physical memory address space.

10. The non-transitory computer readable medium of claim 9 , wherein mapping comprises a set of instructions for using the address mapping function in the IOMMU.

11. The method of claim 1 , further comprising:

generating an error if access of a memory address outside of the domain is detected.

12. The method of claim 11 , further comprising:

correlating the error with a device that is accessing the memory address outside of the domain.

13. The method of claim 1 , further comprising:

displaying an error notification on a GUI if access of a memory address outside of the domain is detected.

14. The method of claim 1 , further comprising:

testing the PCie device via a test system or application platform.

15. The non-transitory computer readable medium of claim 6 , further comprising:

generating an error if access of a memory address outside of the domain is detected.

16. The non-transitory computer readable medium of claim 15 , further comprising:

correlating the error with the PCie device that is accessing the memory address outside of the domain.

17. The non-transitory computer readable medium of claim 6 , further comprising:

displaying an error notification on a GUI if access of a memory address outside of the domain is detected.

18. The non-transitory computer readable medium of claim 6 , further comprising:

testing the PCie device via a test system or application platform.

19. A memory space violation detection system comprising:

one or more target test devices;

an I/O Memory Management Unit (IOMMU) connected to the one or more target test devices via an I/O bus connection, the IOMMU comprising:

a virtual memory address space that defines a memory address fence to limit memory access of the one or more target test devices to specified address spaces; and

a physical memory address space, mapped via an address mapping function, from the one or more specified address spaces accessed by the target test devices; and

a physical memory, connected to the IOMMU via a system memory bus, wherein the physical memory includes physical memory locations for data from the one or more target test devices;

a processor configured to:

monitor direct memory access (DMA) for accesses by the device to memory space outside of the memory address fence; and

detecting a DMA memory address violation by the device.