Polar code encoding method and apparatus
The present disclosure relates to polar code encoding methods and apparatus. One example method includes separately performing check encoding on the at least two to-be-checked first bit sequences to obtain at least two check bit sequences, where a union set of the at least two to-be-checked first bit sequences includes the K information bits, and K is a positive integer, interleaving the K information bits and the at least two check bit sequences, or interleaving a first part of information bit sequence and a first check bit sequence to obtain an interleaved third bit sequence, where a second check bit sequence, a third check bit sequence, and a second part of information bit sequence in a sequence of all information bits except the first part of information bit sequence form a second bit sequence, and performing polar encoding on the second bit sequence.
1. A polar code encoding method, comprising:
separately performing check encoding on at least two to-be-checked first bit sequences to obtain at least two check bit sequences, wherein a union set of the at least two to-be-checked first bit sequences comprises K information bits, and wherein K is a positive integer;
interleaving the K information bits and the at least two check bit sequences to obtain a second bit sequence, or interleaving a first part of information bit sequence and a first check bit sequence to obtain an interleaved third bit sequence, wherein a second check bit sequence, a third check bit sequence, and a second part of information bit sequence in a sequence of all information bits except the first part of information bit sequence form the second bit sequence; and
performing polar encoding on the second bit sequence.
2. The method according to claim 1 , wherein the at least two to-be-checked first bit sequences comprise:
the first part of information bit sequence with a length of K 1 and the sequence of all information bits with a length of K, wherein K 1 <K, and K 1 and K are both positive integers.
3. The method according to claim 2 , wherein the separately performing check on the at least two to-be-checked first bit sequences to obtain at least two check bit sequences comprises:
performing check encoding on the first part of information bit sequence to obtain the first check bit sequence; and
performing check encoding on the sequence of all information bits to obtain the second check bit sequence.
4. The method according to claim 1 , wherein an interleaved sequence S used to perform the interleaving operation comprises J subsequences, and an i th subsequence comprises a location index value of an element 1 in an immediate result vector T i and a value of (K+i), wherein 1≤i≤J, i is an integer, T i =(˜M) & (V i ), M=M|(V i ), M represents a mask vector, V i represents a column vector of a check part matrix P, P represents a submatrix of a systematic generator matrix G of check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AND operation, and represents a bit-by-bit OR operation.
5. A polar code encoding method, comprising:
performing check encoding on an empty set bit sequence with a length of 0 to obtain a first check bit sequence, and performing check encoding on K information bits to obtain a second check bit sequence;
interleaving the K information bits, the first check bit sequence, and the second check bit sequence; and performing polar encoding on a sequence obtained after the interleaving operation.
6. The method according to claim 5 , wherein the first check bit sequence is an all-zero vector.
7. The method according to claim 5 , wherein an interleaved sequence S used to perform the interleaving operation comprises J subsequences, and an i th subsequence comprises a location index value of an element 1 in an immediate result vector T i and a value of (K+i), wherein 1≤i≤J, i is an integer, T i =(˜M) & (V i ), M=M|(V i ), M represents a mask vector, V i represents a column vector of a check part matrix P, P represents a submatrix of a systematic generator matrix G of check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AND operation, and | represents a bit-by-bit OR operation.
8. A polar code encoding apparatus, comprising:
a check unit, configured to separately perform check encoding on at least two to-be-checked first bit sequences to obtain at least two check bit sequences, wherein a union set of the at least two to-be-checked first bit sequences comprises K information bits, and wherein K is a positive integer;
an interleaving unit, configured to interleave the K information bits and the at least two check bit sequences to obtain a second bit sequence, or interleave a first part of information bit sequence and a first check bit sequence to obtain an interleaved third bit sequence, wherein a second check bit sequence, a third check bit sequence, and a second part of information bit sequence in a sequence of all information bits except the first part of information bit sequence form the second bit sequence; and
an encoding unit, configured to perform polar encoding on the second bit sequence.
9. The apparatus according to claim 8 , wherein the at least two to-be-checked first bit sequences comprise:
a first part of information bit sequence with a length of K 1 , and the sequence of all information bits with a length of K, wherein K 1 <K, and K 1 and K are both positive integers.
10. The apparatus according to claim 9 , wherein the check unit is configured to:
perform check encoding on the first part of information bit sequence to obtain the first check bit sequence; and
perform check encoding on the sequence of all information bits to obtain the second check bit sequence.
11. The apparatus according to claim 8 , wherein an interleaved sequence S used by the interleaving unit to perform the interleaving operation comprises J subsequences, and an i th subsequence comprises a location index value of an element 1 in an immediate result vector T i and a value of (K+i), wherein 1≤i≤J, i is an integer, T i =(˜M) & (V i ), M=M|(V i ), M represents a mask vector, V i represents a column vector of a check part matrix P, P represents a submatrix of a systematic generator matrix G of check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AM) operation, and | represents a bit-by-bit OR operation.
12. A polar code encoding apparatus, comprising:
at least one processor; and
a non-transitory computer-readable storage medium coupled to the at least one processor and storing programming instructions for execution by the at least one processor, wherein the programming instructions instruct the at least one processor to:
perform check encoding on an empty set bit sequence with a length of 0 to obtain a first check bit sequence, and perform check encoding on K information bits to obtain a second check bit sequence;
interleave the K information bits, the first check bit sequence; and the second check bit sequence; and
perform polar encoding on a sequence obtained after the interleaving operation.
13. The apparatus according to claim 12 , wherein the first check bit sequence is an all-zero vector.
14. The apparatus according to claim 12 , wherein an interleaved sequence S used to perform the interleaving operation comprises subsequences, and an i th subsequence comprises a location index value of an element 1 in an immediate result vector T i and a value of (K+i), wherein 1≤i≤j, i is an integer, T i =(˜M) & (V i ), M=M|(V i ), M represents a mask vector, Vi represents a column vector of a check part matrix P, P represents a submatrix of a systematic generator matrix G of check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AND operation, and | represents a bit-by-bit OR operation.
15. A polar code encoding apparatus, comprising:
at least one processor; and
a non-transitory computer-readable storage medium coupled to the at least one processor and storing programming instructions for execution by the at least one processor, wherein the programming instructions instruct the at least one processor to:
separately perform check encoding on at least two to-be-checked first bit sequences to obtain at least two check bit sequences, wherein a union set of the at least two to-be-checked first bit sequences comprises K information bits, and wherein K is a positive integer;
interleave the K information bits and the at least two check bit sequences to obtain a second bit sequence, or interleave a first part of information bit sequence a the first check bit sequence to obtain an interleaved third bit sequence, wherein a second check bit sequence; a third check bit sequence, and a second part of information bit sequence in a sequence of all information bits except the first part of information bit sequence form the second bit sequence; and
perform polar encoding on the second bit sequence.
16. The apparatus according to claim 15 , wherein the at least two to-be-checked first bit sequences comprise the first part of information bit sequence with a length of K 1 and the sequence of all information bits with a length of K, wherein K 1 <K, and wherein K 1 and K are both positive integers.
17. The apparatus according to claim 15 , wherein the programming instructions instruct the at least one process to:
perform check encoding on the first part of information bit sequence to obtain the first check bit sequence; and
perform check encoding on the sequence of all information bits to obtain the second check bit sequence.
18. The apparatus according to claim 15 , wherein an interleaved sequence S used to perform the interleaving operation comprises subsequences, and an i th subsequence comprises a location index value of an element 1 in an immediate result vector T i and a value of (K+i), wherein 1≤i≤J, i is an integer, T i , (˜M) & (V i ), M=M|(V i ), M represents a mask vector, V i represents a column vector of a check part matrix P, P represents a submatrix of a systematic generator matrix G of check encoding, ˜ represents a bit-by-bit NOT operation, & represents a bit-by-bit AND operation, and | represents a bit-by-bit OR operation.
19. The apparatus according to claim 15 , wherein the apparatus is a chip or an integrated circuit.