Vector processor for heterogeneous data streams
A vector processor includes a grouping memory functional unit coupled to grouping memory having multiple bins. The vector processor also includes a bitformatting functional unit that performs bit-level data arrangements using any suitable technique or network, such as a Benes network. The vector processor receives and reads an input vector of data that includes portions (e.g., bits) of multiple data streams, and writes each portion corresponding to a respective data stream to a respective bin in parallel using the bitformatting functional unit to align the data. The vector processor also or alternatively receives and reads multiple outgoing data streams, writes portions of the data streams in respective bins of the grouping memory, and intersperses the portions in an outgoing vector of data in parallel, using the bitformatting functional unit to align the data.
1. A vector processor to receive a vector of heterogeneous data from or send the vector of heterogeneous data to a device, wherein the heterogeneous data includes a plurality of data samples, at least some of the data samples of the plurality of data samples having different data types, formats, alignments, or any combination thereof, and wherein the vector processor comprises:
a grouping memory comprising a plurality of bins to store a plurality of aligned data samples of a plurality of homogeneous data streams, wherein each homogeneous data stream of the plurality of homogeneous data streams comprises a same data type, format, alignment or any combination thereof;
bitformatting circuitry to:
associate each data sample of the plurality of data samples in the vector of heterogeneous data with a corresponding homogeneous data stream of the plurality of homogeneous data streams; and
align each data sample of the plurality of data samples belonging to a same homogeneous data stream of the plurality of homogeneous data streams to generate the plurality of aligned data samples; and
grouping memory circuitry to write the plurality of aligned data samples to corresponding bins of the plurality of bins in parallel.
2. The vector processor of claim 1 , wherein the vector processor is to receive the plurality of data samples in one or more input vectors.
3. The vector processor of claim 2 , wherein an input vector of the one or more input vectors is one byte in size.
4. The vector processor of claim 1 , wherein at least one data sample of the plurality of data samples is one bit in size.
5. The vector processor of claim 1 , wherein at least one bin of the plurality of bins is one byte in size.
6. The vector processor of claim 1 , comprising a control pattern table to store a plurality of formatting types or specifications of the plurality of homogeneous data streams, wherein the bitformatting circuitry is to associate the plurality of data samples with the plurality of homogeneous data streams based on the plurality of formatting types or specifications stored in the control pattern table.
7. The vector processor of claim 1 , comprising a plurality of single input multiple data circuitries to perform arithmetic operations, logic operations, or any other data processing operations.
8. An integrated circuit comprising:
processing circuitry to receive a first vector of first heterogeneous data from a first device apart from the integrated circuit, and send a second vector of second heterogeneous data to a second apart from the integrated circuit; and
vector processing circuitry to:
receive the first vector of first heterogeneous data and generate first homogeneous data streams from the first vector of first heterogeneous data in parallel; and
receive second homogenous data streams in parallel and generate the second vector of second heterogeneous data.
9. The integrated circuit of claim 8 , wherein the vector processing circuitry comprises a plurality of bins to store samples of the first homogeneous data streams.
10. The integrated circuit of claim 9 , wherein the vector processing circuitry reads the samples from the plurality of bins and write the samples to an output vector in parallel.
11. The integrated circuit of claim 8 , wherein a homogeneous data stream comprises a set of samples having the same size, alignment, format, or any combination thereof.
12. The integrated circuit of claim 8 , wherein the vector processing circuitry comprises single input multiple data very large instruction word processors that enable the vector processing circuitry to perform parallel processing techniques on the first vector of first heterogeneous data or the first homogeneous data streams.
13. The integrated circuit of claim 8 , wherein the vector processing circuitry employs a control header to implement data processing loop techniques to generate the first homogeneous data streams.
14. The integrated circuit of claim 13 , wherein the control header comprises:
a set of control inputs for instructions to be executed by the vector processing circuitry; and
pointers to input data and output data.
15. A vector processor comprising:
grouping memory circuitry;
a grouping memory comprising a plurality of bins; and
bitformatting circuitry, wherein the vector processor is to receive a first data sample in a first data arrangement and provide the first data sample in a second data arrangement different from the first data arrangement with respect to one or more data types, formats, alignments, or any combination thereof of the first data sample after execution by the bitformatting circuitry, the grouping memory, and the grouping memory circuitry.
16. The vector processor of claim 15 , wherein the first data arrangement comprises a plurality of data samples from a plurality of different data streams, wherein the plurality of data samples comprises the first data sample.
17. The vector processor of claim 16 , wherein the plurality of bins comprises a set of bins corresponding to the plurality of different data streams.
18. The vector processor of claim 15 , wherein the grouping memory circuitry removes data samples stored in a bin of the plurality of bins when storage of the bin exceeds a threshold storage amount.
19. The vector processor of claim 18 , wherein the threshold storage amount comprises a storage capacity of the bin.
20. The vector processor of claim 15 , wherein the bitformatting circuitry comprises a Benes network.
21. The vector processor of claim 20 , wherein the Benes network is to provide the first data sample in the second data arrangement different from the first data arrangement by permuting the first data sample to predetermined boundaries.