Detecting a dynamic control flow re-convergence point for conditional branches in hardware
Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.
1. A processor core comprising:
a decoder to decode instructions into decoded instructions;
an execution unit to execute the decoded instructions;
a branch predictor circuit to predict a future outcome of a branch instruction; and
a branch predication manager circuit to disable use of the predicted future outcome, that has been generated by the branch predictor circuit, for a conditional critical branch comprising the branch instruction.
2. The processor core of claim 1 , wherein the branch predication manager circuit is to detect the conditional critical branch, and then determine a point of re-convergence for the conditional critical branch.
3. The processor core of claim 2 , further comprising an instruction fetch unit, and the branch predication manager circuit causes the instruction fetch unit to fetch instructions of both a taken portion and a not-taken portion of the conditional critical branch up to the point of re-convergence.
4. The processor core of claim 3 , wherein the branch predication manager circuit is to cause the taken portion of the conditional critical branch to be architecturally visible after detecting the branch instruction of the conditional critical branch is executed by the execution unit.
5. The processor core of claim 3 , wherein the branch predication manager circuit is to increment a counter for every mispredicted instance of the branch instruction that triggers a pipeline flush, and disable use of the predicted future outcome for the conditional critical branch comprising the branch instruction when the counter exceeds a threshold.
6. The processor core of claim 3 , wherein the branch predication manager circuit is to determine if the conditional critical branch is one of a plurality of possible convergence patterns, and cause the instruction fetch unit to fetch the instructions of both the taken portion and the not-taken portion of the conditional critical branch up to the point of re-convergence in response to the conditional critical branch being one of the plurality of possible convergence patterns.
7. The processor core of claim 1 , wherein the branch predication manager circuit is to determine that a conditional branch is the critical conditional branch when the conditional branch exceeds a minimum threshold of misprediction events in an observation window of retired instructions.
8. The processor core of claim 1 , wherein the branch predication manager circuit is to throttle disabling of the use of the predicted future outcome based at least in part on a comparison of performance for a first proper subset of a plurality of retired instances of the conditional critical branch where the branch predication manager circuit is allowed to disable use of the predicted future outcome and performance for a second proper subset of the plurality of retired instances of the conditional critical branch where the branch predication manager circuit is not allowed to disable use of the predicted future outcome.
9. A method comprising:
decoding instructions into decoded instructions with a decoder of a hardware processor;
executing the decoded instructions with an execution unit of the hardware processor;
predicting a future outcome of a branch instruction with a branch predictor circuit of the hardware processor; and
disabling use of the predicted future outcome, that has been generated by the branch predictor circuit, for a conditional critical branch comprising the branch instruction with a branch predication manager circuit of the hardware processor.
10. The method of claim 9 , further comprising detecting the conditional critical branch with the branch predication manager circuit, and then determining a point of re-convergence for the conditional critical branch with the branch predication manager circuit.
11. The method of claim 10 , further comprising causing, by the branch predication manager circuit, an instruction fetch unit of the hardware processor to fetch instructions of both a taken portion and a not-taken portion of the conditional critical branch up to the point of re-convergence.
12. The method of claim 11 , further comprising causing, by the branch predication manager circuit, the taken portion of the conditional critical branch to be architecturally visible after detecting the branch instruction of the conditional critical branch is executed by the execution unit.
13. The method of claim 11 , further comprising:
incrementing a counter for every mispredicted instance of the branch instruction that triggers a pipeline flush; and
disabling use of the predicted future outcome for the conditional critical branch comprising the branch instruction when the counter exceeds a threshold.
14. The method of claim 11 , further comprising:
determining, by the branch predication manager circuit, if the conditional critical branch is one of a plurality of possible convergence patterns, and
causing the instruction fetch unit to fetch the instructions of both the taken portion and the not-taken portion of the conditional critical branch up to the point of re-convergence in response to the conditional critical branch being one of the plurality of possible convergence patterns.
15. The method of claim 9 , further comprising determining, by the branch predication manager circuit, that a conditional branch is the critical conditional branch when the conditional branch exceeds a minimum threshold of misprediction events in an observation window of retired instructions.
16. The method of claim 9 , further comprising throttling disabling of the use of the predicted future outcome, by the branch predication manager circuit, based at least in part on a comparison of performance for a first proper subset of a plurality of retired instances of the conditional critical branch where the branch predication manager circuit is allowed to disable use of the predicted future outcome and performance for a second proper subset of the plurality of retired instances of the conditional critical branch where the branch predication manager circuit is not allowed to disable use of the predicted future outcome.
17. A non-transitory machine readable medium that stores program code that when executed by a machine causes the machine to perform a method comprising:
decoding instructions into decoded instructions with a decoder of a hardware processor;
executing the decoded instructions with an execution unit of the hardware processor;
predicting a future outcome of a branch instruction with a branch predictor circuit of the hardware processor; and
disabling use of the predicted future outcome, that has been generated by the branch predictor circuit, for a conditional critical branch comprising the branch instruction with a branch predication manager circuit of the hardware processor.
18. The non-transitory machine readable medium of claim 17 , further comprising detecting the conditional critical branch with the branch predication manager circuit, and then determining a point of re-convergence for the conditional critical branch with the branch predication manager circuit.
19. The non-transitory machine readable medium of claim 18 , further comprising causing, by the branch predication manager circuit, an instruction fetch unit of the hardware processor to fetch instructions of both a taken portion and a not-taken portion of the conditional critical branch up to the point of re-convergence.
20. The non-transitory machine readable medium of claim 19 , further comprising causing, by the branch predication manager circuit, the taken portion of the conditional critical branch to be architecturally visible after detecting the branch instruction of the conditional critical branch is executed by the execution unit.
21. The non-transitory machine readable medium of claim 19 , further comprising:
incrementing a counter for every mispredicted instance of the branch instruction that triggers a pipeline flush; and
disabling use of the predicted future outcome for the conditional critical branch comprising the branch instruction when the counter exceeds a threshold.
22. The non-transitory machine readable medium of claim 19 , further comprising:
determining, by the branch predication manager circuit, if the conditional critical branch is one of a plurality of possible convergence patterns, and
causing the instruction fetch unit to fetch the instructions of both the taken portion and the not-taken portion of the conditional critical branch up to the point of re-convergence in response to the conditional critical branch being one of the plurality of possible convergence patterns.
23. The non-transitory machine readable medium of claim 17 , further comprising determining, by the branch predication manager circuit, that a conditional branch is the critical conditional branch when the conditional branch exceeds a minimum threshold of misprediction events in an observation window of retired instructions.
24. The non-transitory machine readable medium of claim 17 , further comprising throttling disabling of the use of the predicted future outcome, by the branch predication manager circuit, based at least in part on a comparison of performance for a first proper subset of a plurality of retired instances of the conditional critical branch where the branch predication manager circuit is allowed to disable use of the predicted future outcome and performance for a second proper subset of the plurality of retired instances of the conditional critical branch where the branch predication manager circuit is not allowed to disable use of the predicted future outcome.