Method for reading three-dimensional flash memory
A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (V prepare ) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (V off ) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (V pass ) on an unselected word line (Unsel_WL).
1. A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device, comprising:
removing fast charges of the target memory cell at a read-prepare step, comprising:
applying a prepare voltage (V prepare ) on an unselected top select gate (Unsel_TSG) of an unselected memory string;
applying a first off voltage (V off ) on a selected word line (Sel_WL) associated with the target memory cell; and
applying a pass voltage (V pass ) on an unselected word line (Unsel_WL); and
measuring a threshold voltage of the target memory cell at a sensing step.
2. The method of claim 1 , further comprising:
applying a top select gate voltage (V tsg ) on a selected top select gate (Sel_TSG) of a selected memory string containing the target memory cell; and
applying a lower select gate voltage (V lsg ) on a lower select gate (LSG) of the selected memory string containing the target memory cell.
3. The method of claim 2 , wherein applying the top select gate voltage (V tsg ) comprises electrically connecting the selected memory string to a bit line; and applying the lower select gate voltage (V lsg ) comprises electrically connecting the selected memory string to an array common source.
4. The method of claim 2 , wherein applying the top select gate voltage (V tsg ) comprises applying a voltage between 4V to 7V.
5. The method of claim 2 , wherein applying the lower select gate voltage (V lsg ) comprises applying a voltage between 4V to 7V.
6. The method of claim 2 , wherein applying the pass voltage (V pass ) comprises applying the pass voltage with a delay period after the selected top select gate (Sel_TSG) and the lower select gate (LSG) are at the top select gate voltage (V tsg ) and the lower select gate voltage (V lsg ), respectively.
7. The method of claim 1 , wherein measuring the threshold voltage comprises applying a read voltage (V read ) on the selected word line (Sel_WL).
8. The method of claim 7 , wherein applying the read voltage (V read ) comprises applying a voltage between 0 to 2V.
9. The method of claim 7 , wherein applying the read voltage (V read ) comprises applying a second off voltage on the unselected word line (Unsel_WL).
10. The method of claim 9 , wherein applying the second off voltage on the unselected word line (Unsel_WL) comprises applying a 0V.
11. The method of claim 7 , wherein applying the read voltage (V read ) comprises applying the read voltage (V read ) when a voltage of the unselected top select gate (Unsel_TSG) is higher than a threshold voltage of an unselected memory cell.
12. The method of claim 7 , wherein applying the read voltage (V read ) comprises applying the read voltage (V read ) when a voltage of the unselected top select gate (Unsel_TSG) equals to a threshold voltage of an unselected memory cell.
13. The method of claim 7 , wherein applying the read voltage (V read ) comprises applying the read voltage (V read ) when a voltage of the unselected top select gate (Unsel_TSG) is lower than a threshold voltage of an unselected memory cell.
14. The method of claim 1 , wherein applying the prepare voltage (V prepare ) comprises applying a voltage between 4V to 7V.
15. The method of claim 1 , wherein applying the first off voltage (V off ) comprises applying a 0V.
16. The method of claim 1 , wherein applying the pass voltage (V pass ) comprises applying a voltage between 5V to 9V.
17. The method of claim 1 , wherein removing the fast charges comprises removing the fast charges from a storage layer of the target memory cell of a selected memory string, wherein the selected memory string comprises:
a channel hole penetrating vertically through a film stack of alternating conductive and dielectric layers;
a core filling film in a center of the channel hole;
a memory film covering a sidewall of the channel hole, wherein the memory film comprises a barrier layer, the storage layer and a tunneling layer; and
a channel layer sandwiched between the memory film and the core filling film.
18. The method of claim 17 , wherein removing the fast charges comprises removing electrical charges from shallow traps in the storage layer of the target memory cell.
19. The method of claim 17 , wherein removing the fast charges comprises removing the fast charges from the target memory cell to a neighboring unselected memory cell.
20. The method of claim 1 , wherein conducting the read-verification operation comprises conducting the read-prepare step and conducting a failed bit count in parallel.