Semiconductor device and manufacturing method therefore

1. A method of manufacturing a field effect transistor (FET), the method comprising:

forming a sacrificial region in a substrate, the sacrificial region including a first part and a second part separated by a first part of the substrate from the second part in a cross section of a source-to-drain direction of the FET, the sacrificial region having a higher impurity concentration than the first part of the substrate;

forming a trench in the substrate by etching the sacrificial region and a second part of the substrate below the sacrificial region, a part of the sacrificial region being exposed in the trench;

forming a space by partially etching the sacrificial region, wherein a part of the sacrificial region remains;

forming an isolation insulating layer in the trench and the space to contact the remaining part of the sacrificial region; and

forming a gate structure including a gate dielectric layer and a gate electrode formed on the gate dielectric layer over the first part of the substrate and a source/drain region,

wherein an air spacer is formed in the space under the source/drain region.

2. The method of claim 1 , wherein the sacrificial region is formed by an ion implantation operation.

3. The method of claim 2 , wherein ions of arsenic are implanted by the ion implantation operation.

4. The method of claim 2 , wherein a dose amount in the ion implantation operation is in a range from 5×10 13 ions/cm 2 to 5×10 15 ions/cm 2 .

5. The method of claim 2 , wherein an acceleration voltage in the ion implantation operation is in a range from 0.5 keV to 10 keV.

6. The method of claim 1 , wherein the space has a rectangular shape.

7. The method of claim 1 , wherein the partially etching the sacrificial region comprises a dry etching operation using a chlorine containing gas.

8. The method of claim 1 , wherein the space has a triangular or a trapezoid shape.

9. The method of claim 8 , wherein the partially etching the sacrificial region comprises a wet etching operation using a tetramethylammonium hydroxide (TMAH) aqueous solution.

10. The method of claim 9 , wherein one surface defining the space has a zig-zag surface.

11. The method of claim 1 , wherein the air spacer is partially enclosed by an insulating material of the isolation insulating layer.

12. The method of claim 1 , wherein the air spacer is fully enclosed by an insulating material of the isolation insulating layer.

13. The method of claim 1 , wherein an impurity containing region containing an impurity in an amount higher than the substrate is disposed between the space and the substrate.

14. A method of manufacturing a FET, the method comprising:

forming a sacrificial region in a substrate, the sacrificial region including a first part and a second part separated by a first part of the substrate from the second part in a cross section of a source-to-drain direction of the FET, the sacrificial region having a higher impurity concentration than the first part of the substrate;

forming an epitaxial semiconductor layer over the substrate;

forming a trench by etching part of the epitaxial semiconductor layer, the sacrificial region and a second part of the substrate below the sacrificial region, wherein a part of the sacrificial region is exposed in the trench;

forming a space by laterally etching the sacrificial region, wherein a part of the sacrificial region remains;

forming an insulating material layer in the trench and the space to contact the remaining part of the sacrificial region; and

forming a gate structure including a gate dielectric layer and a gate electrode formed on the gate dielectric layer over the first part of the substrate and a source/drain region,

wherein an air spacer is formed in the space under the source/drain region.

15. The method of claim 14 , wherein the sacrificial region is formed by an ion implantation operation.

16. The method of claim 15 , wherein an impurity amount of the sacrificial region is in a range from 1×10 19 atoms/cm 3 to 5×10 21 atoms/cm 3 .

17. The method of claim 15 , wherein a thickness of the epitaxial semiconductor layer is in a range from 5 nm to 100 nm.

18. The method of claim 14 , wherein:

the gate structure extends in a first direction, and

a width of the air spacer varies along the first direction in plan view.

19. The method of claim 14 , wherein:

the gate structure extends in a first direction, and

the air spacer is discontinuous under the source/drain region along the first direction in plan view.

20. A method of manufacturing a FET, the method comprising:

forming sacrificial regions in a substrate, the sacrificial region including a first part and a second part separated by a first part of the substrate from the second part in a cross section of a source-to-drain direction of the FET, the sacrificial region having a higher impurity concentration than the first part of the substrate;

forming an epitaxial semiconductor layer over the substrate;

forming a trench surrounding an active region by etching part of the epitaxial semiconductor layer, the sacrificial regions and a second part of the substrate below the sacrificial region, wherein a part of the sacrificial region is exposed in the trench;

forming spaces by partially etching the sacrificial region to that a part of the sacrificial region remains;

forming an insulating material layer in the trench and the spaces to contact the remaining part of the sacrificial region; and

forming gate structures including a gate dielectric layer and a gate electrode formed on the gate dielectric layer over the first part of the substrate and source/drain regions over the active region,

wherein air spacers are formed in the spaces under the source/drain regions, respectively.