IP Library › Granted Patent US 11,488,984
Granted Patent B2
US 11,488,984 · App. 16/733,435 · Granted Nov 1, 2022

Wiring structure, semiconductor device and display device

Inventor: Yohei Yamaguchi (Tokyo, JP)
Assignee: Japan Display Inc.
H01L27/124G02F1/133345G02F1/136227G02F1/136286H01L21/02554H01L21/02565H01L21/31116H01L21/822H01L27/1225G02F1/136295G02F2201/123
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Quick Facts
Patent No.
US 11,488,984
App. No.
16/733,435
Granted
Nov 1, 2022
Kind
B2
Abstract

A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.

Claims (22)

1. A wiring structure comprising:

a structure body including a pattern;

a first conductive layer above the structure body;

a first insulating layer above the first conductive layer, wherein the first insulating layer has a first opening; and

a second conductive layer in the first opening,

wherein

the first conductive layer has a shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body,

the first opening of the first insulating layer overlaps the edge of the pattern of the structure body in a plan view,

the second conductive layer is connected to the first conductive layer,

the structure body is an oxide semiconductor,

the first conductive layer is a source electrode or a drain electrode of a transistor,

the first conductive layer includes a first film, a second film below the first film, and a third film below the second film,

a part of a surface of the first film on the second film side is exposed from the second film, and

the second conductive layer directly contacts the third film at the first opening;

wherein a gap is arranged between the second film and the second conductive layer; and

further comprising:

a second insulating layer below the structure body; and

a semiconductor layer below the second insulting layer, the semiconductor layer being arranged in a region not overlapping the first opening in the plan view;

wherein

the structure body includes a first oxide semiconductor layer connected to the first conductive layer,

the first insulating layer has a second opening in a region overlapping the semiconductor layer in the plan view, and

the second insulating layer has a third opening in a region overlapping the second opening in the plan view.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: YAMAGUCHI, YOHEI
To: JAPAN DISPLAY INC.
Reel/Frame 051408/0186 →
Priority Claims (1)
JP JP2019-002537 · Jan 10, 2019 · national
Continuity (1)
Related Publication 20200227443A1 · Jul 16, 2020