Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple

1. A method for fabricating a semiconductor device, comprising:

forming a three-dimensional monolithic vertical transistor memory cell with a unified inter-tier cross-couple, including:

connecting a first tier including a contact disposed on a first inverter gate to a second tier including a second inverter gate by forming a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate, including forming a ground contact connecting the second tier to a bottom source/drain region of the first tier.

2. The method of claim 1 , wherein the first tier includes a plurality of n-type vertical transistors and the second tier includes a plurality of p-type vertical transistors.

3. The method of claim 1 , wherein the vertical transistor device includes a six-transistor memory cell.

4. The method of claim 3 , wherein the first tier includes two vertical transistors and the second tier includes four vertical transistors.

5. The method of claim 1 , further comprising forming the first tier.

6. The method of claim 1 , further comprising forming the second tier.

7. The method of claim 6 , wherein forming the second tier further includes transferring, on the first tier, a layer of semiconductor material for forming the second tier using wafer bonding.

8. The method of claim 7 , wherein the wafer bonding includes oxide-oxide wafer bonding.

9. A method for fabricating a semiconductor device, comprising:

forming a three-dimensional monolithic vertical transistor memory cell with a unified inter-tier cross-couple, including:

connecting a first tier including a plurality of first vertical transport field-effect transistors (VTFETs) associated with a first conductivity type and a contact disposed on a first inverter gate to a second tier including a plurality of second VTFETs associated with a second conductivity type and a second inverter gate by forming a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate, including forming a ground contact connecting the second tier to a bottom source/drain region of the first tier.

10. The method of claim 9 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. The method of claim 9 , wherein the vertical transistor device includes a six-transistor memory cell.

12. The method of claim 11 , wherein the first tier includes two vertical transistors and the second tier includes four vertical transistors.

13. The method of claim 9 , further comprising forming the first tier.

14. The method of claim 9 , further comprising forming the second tier.

15. The method of claim 14 , wherein forming the second tier further includes transferring, on the first tier, a layer of semiconductor material for forming the second tier using oxide-oxide wafer bonding.

16. A semiconductor device comprising:

a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple, including:

a first tier including a contact disposed on a first inverter gate;

a second tier including a second inverter gate;

a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate; and

a ground contact connecting the second tier to a bottom source/drain region of the first tier.

17. The device of claim 16 , wherein the first tier includes two vertical transistors and the second tier includes four vertical transistors.

18. The device of claim 16 , wherein the first tier includes a plurality of n-type transistors and the second tier includes a plurality of p-type transistors.

19. The device of claim 16 , wherein the first tier and the second tier each include a plurality of vertical transistors.

20. The device of claim 16 , wherein the vertical transistor device includes a six-transistor memory cell.