Method for analyzing electromigration (EM) in integrated circuit
Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.
1. A method for analyzing electromigration (EM) in an integrated circuit (IC), comprising:
obtaining a layout of the IC;
selecting a metal segment from the layout according to a current simulation result of the IC; and
determining whether to relax EM rule on the metal segment according to the number of vias over the metal segment in the layout and current direction of each of the vias,
wherein the vias are in contact with the metal segment.
2. The method as claimed in claim 1 , wherein determining whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout and the current direction of each of the vias further comprises:
determining whether two vias are formed over and in contact with the metal segment; and
determining whether a distance between the two vias is less than a threshold distance.
3. The method as claimed in claim 2 , wherein the two vias are positioned at two sides of the metal segment.
4. The method as claimed in claim 2 , wherein determining whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout and the current direction of each of the vias further comprises:
determining whether the two vias have the same current direction according to the current simulation result of the IC when the distance between the two vias is less than the threshold distance; and
decreasing EM severity ration of the metal segment when the two vias have the same current direction.
5. The method as claimed in claim 4 , wherein the metal segment is a power net, and the two vias have the downward current direction.
6. The method as claimed in claim 4 , wherein the metal segment is a ground net, and the two vias have the upward current direction.
7. The method as claimed in claim 4 , wherein the metal segment is a signal net, and the two vias have the downward or upward current direction.
8. The method as claimed in claim 1 , further comprising:
keeping the EM rule on the metal segment when a single via is formed over the metal segment.
9. A method for analyzing electromigration (EM) in an integrated circuit (IC), comprising:
obtaining a layout of the IC;
selecting a first via over a metal segment from the layout according to a current simulation result of the IC; and
determining whether to relax EM rule on the first via according to the number of second vias over the metal segment in the layout and current direction of each of the first and second vias,
wherein the first and second vias are in contact with the metal segment.
10. The method as claimed in claim 9 , wherein determining whether to relax the EM rule on the first via according to the number of second vias over the metal segment and the current direction of each of the first and second vias further comprises:
determining whether two second vias are formed over the metal segment and on both sides of the first via in the layout; and
determining whether a distance between the first via and each of the two second vias is less than a threshold distance.
11. The method as claimed in claim 10 , wherein the two second vias are positioned at two sides of the metal segment.
12. The method as claimed in claim 10 , wherein determining whether to relax the EM rule on the first via according to the number of second vias over the metal segment in the layout and the current direction of each of the first and second vias further comprises:
determining whether the first via and the second vias have the same current direction according to the current simulation result of the IC when the distance between the first via and each of the second vias is less than the threshold distance; and
decreasing EM severity ration of the first via when the first via and the second vias have the same current direction.
13. The method as claimed in claim 12 , wherein the metal segment is a power net, and the first via and the second vias have the downward current direction.
14. The method as claimed in claim 12 , wherein the metal segment is a ground net, and the first via and the second vias have the upward current direction.
15. The method as claimed in claim 12 , wherein the metal segment is a signal net, and the first via and the second vias have the downward or upward current direction.
16. The method as claimed in claim 9 , further comprising:
keeping the EM rule on the first via when a single second via is formed over the metal segment.
17. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for analyzing electromigration (EM) in an integrated circuit (IC), the method comprising:
obtaining a layout of the IC;
selecting a metal segment from the layout according to a current simulation result of the IC; and
determining whether to relax EM rule on the metal segment according to the number of vias over the metal segment in the layout and current direction of each of the vias,
wherein the vias are in contact with the metal segment.
18. The non-transitory computer-readable storage medium as claimed in claim 17 , wherein determining whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout and the current direction of each of the vias further comprises:
determining whether two vias are formed over and in contact with the metal segment; and
determining whether a distance between the two vias is less than a threshold distance.
19. The non-transitory computer-readable storage medium as claimed in claim 18 , wherein determining whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout and the current direction of each of the vias further comprises:
determining whether the two vias have the same current direction according to the current simulation result of the IC when the distance between the two vias is less than the threshold distance; and
decreasing EM severity ration of the metal segment when the two vias have the same current direction.
20. The non-transitory computer-readable storage medium as claimed in claim 17 , further comprising:
keeping the EM rule on the metal segment when a single via is formed over the metal segment.