Scalable integration of hybrid optoelectronic and quantum optical systems into photonic circuits
A process is provided for the high-yield heterogeneous integration of ‘quantum micro-chiplets’ (QMCs, diamond waveguide arrays containing highly coherent color centers) with an aluminum nitride (AlN) photonic integrated circuit (PIC). As an example, the process is useful for the development of a 72-channel defect-free array of germanium-vacancy (GeV) and silicon-vacancy (SiV) color centers in a PIC. Photoluminescence spectroscopy reveals long-term stable and narrow average optical linewidths of 54 MHz (146 MHz) for GeV (SiV) emitters, close to the lifetime-limited linewidth of 32 MHz (93 MHz). Additionally, inhomogeneities in the individual qubits can be compensated in situ with integrated tuning of the optical frequencies over 100 GHz. The ability to assemble large numbers of nearly indistinguishable artificial atoms into phase-stable PICs is useful for development of multiplexed quantum repeaters and general-purpose quantum computers.
1. A photonic integrated circuit comprising:
a substrate;
a first array of waveguides integrated with the substrate; and
a solid-state chip integrated onto the substrate in alignment with the first array of waveguides and comprising:
an array of quantum emitters, formed in the solid-state chip, to emit single photons; and
a second array of waveguides integrated with the solid-state chip, each waveguide in the second array of waveguides in optical communication with a corresponding quantum emitter in the array of quantum emitters and with a corresponding waveguide in the first array of waveguides to guide the single photons from the corresponding quantum emitter to the corresponding waveguide in the first array of waveguides.
2. The photonic integrated circuit of claim 1 , wherein the solid-state chip defines a first alignment feature mated to a second alignment feature defined by the substrate.
3. The photonic integrated circuit of claim 1 , wherein the solid-state chip is suspended above the substrate, and further comprising:
a pair of electrodes, in electrical communication with the solid-state chip and the substrate, to apply a bias voltage to the solid-state chip with respect to the substrate, the bias voltage straining the solid-state chip, thereby tuning an emission wavelength of at least one quantum emitter in the array of quantum emitters.
4. The photonic integrated circuit of claim 1 , wherein the quantum emitters in the array of quantum emitters are distributed irregularly within the solid-state chip.
5. The photonic integrated circuit of claim 1 , wherein each waveguide in the second array of waveguides has an adiabatically tapered region optically coupled to an adiabatically tapered region of the corresponding waveguide in the first array of waveguides.
6. The photonic integrated circuit of claim 1 , wherein a waveguide in the second array of waveguides is in optical communication with a first quantum emitter and a second quantum emitter in the array of quantum emitters, and further comprising:
a reflector, integrated with the waveguide in the second array of waveguides, to reflect the single photons from the first quantum emitter along the waveguide away from the second quantum emitter and to reflect light from the second quantum emitter along the waveguide away from the first quantum emitter.
7. The photonic integrated circuit of claim 1 , further comprising:
an optical switching network, integrated with the substrate in optical communication with the first array of waveguides, to route at least one of the single photons emitted by the quantum emitters in the array of quantum emitters.
8. The photonic integrated circuit of claim 1 , further comprising:
an array of electrodes, disposed on the solid-state chip in electrical communication with the array of quantum emitters, to apply microwave signals to the array of quantum emitters.
9. The photonic integrated circuit of claim 1 , further comprising a socket formed on the substrate to receive the solid-state chip.
10. The photonic integrated circuit of claim 9 , wherein the solid-state chip further defines a first lock-in feature coupled to a second lock-in feature defined by the socket to secure the solid-state chip on the substrate.
11. A method of making a photonic integrated circuit, the method comprising:
forming a first array of waveguides integrated with a substrate;
forming an array of quantum emitters in a solid-state chip separate from the substrate;
forming a second array of waveguides in the solid-state chip with each waveguide in the second array of waveguides in optical communication with a corresponding quantum emitter in the array of quantum emitters; and
picking and placing the solid-state chip on the substrate such that each quantum emitter in the array of quantum emitters is in optical communication with a corresponding waveguide in the first array of waveguides via a corresponding waveguide in the second array of waveguides.
12. The method of claim 11 , wherein forming the array of quantum emitters comprises forming quantum emitters distributed irregularly within the solid-state chip.
13. The method of claim 11 , wherein picking and placing the solid-state chip on the substrate comprises aligning the solid-state chip to an alignment feature defined by the substrate.
14. The method of claim 11 , wherein picking and placing the solid-state chip on the substrate comprises suspending at least a portion of the solid-state chip above the substrate.
15. The method of claim 14 , further comprising:
forming a first electrode in electrical communication with the solid-state chip; and
forming a second electrode in electrical communication with the substrate and electrically isolated from the first electrode.
16. The method of claim 11 , wherein forming the first array of waveguides comprises forming first adiabatically tapered regions, forming the second array of waveguides comprises forming second adiabatically tapered regions, and integrating the solid-state chip with the substrate comprises aligning the second adiabatically tapered regions to the first adiabatically tapered regions.
17. The method of claim 11 , further comprising:
forming a reflector in optical communication with a waveguide in the second array of waveguides to reflect single photons from the corresponding quantum emitter.
18. The method of claim 11 , further comprising:
forming an optical switching network integrated with the substrate and in optical communication with the first array of waveguides.
19. The method of claim 11 , further comprising:
an array of electrodes, disposed on solid-state chip in electrical communication with the array of quantum emitters, to apply microwave signals to the array of quantum emitters.
20. The method of claim 11 , wherein picking and placing the solid-state chip on the substrate further comprises:
placing the solid-state chip in a socket formed on the substrate; and
locking in the solid-state chip to a lock-in feature defined by the socket to secure the solid-state chip on the substrate.
21. A photonic integrated circuit comprising:
a substrate;
an optical switch network integrated with the substrate;
a first array of waveguides integrated with the substrate in optical communication with the optical switch network;
a first electrode in electrical communication with the substrate; and
a diamond chip suspended over the substrate in alignment with the first array of waveguides and comprising:
an array of quantum emitters, distributed irregularly within the solid-state chip, to emit single photons;
a second array of waveguides integrated with the diamond chip, each waveguide in the second array of waveguides in optical communication with a corresponding quantum emitter in the array of quantum emitters and with a corresponding waveguide in the first array of waveguides to guide the single photons from the corresponding quantum emitter to the optical switch network via the corresponding waveguide in the first array of waveguides; and
a second electrode, in electrical communication with the diamond chip and electrically isolated from the first electrode, to apply a bias voltage across the diamond chip with respect to a potential of the first electrode, the bias voltage straining the diamond chip and tuning an emission wavelength of at least one quantum emitter in the array of quantum emitters.
22. The photonic integrated circuit of claim 21 , wherein the array of quantum emitters comprises at least one of a germanium vacancy, a silicon vacancy, a nitrogen vacancy, or a tin vacancy.
23. The photonic integrated circuit of claim 21 , wherein the diamond chip is a first diamond chip and the array of quantum emitters is a first array of quantum emitters, further comprising:
a third array of waveguides integrated with the substrate;
a second diamond chip suspended over the substrate in alignment with the third array of waveguides and comprising:
a second array of quantum emitters, distributed within the other solid-state chip, to emit single photons;
a fourth array of waveguides integrated with the solid-state chip, each waveguide in the fourth array of waveguides in optical communication with a corresponding quantum emitter in the second array of quantum emitters and with a corresponding waveguide in the third array of waveguides to guide the single photons from the corresponding quantum emitter to the corresponding waveguide in the third array of waveguides.