Die edge integrity monitoring system
An edge crack monitoring system for an integrated circuit provided on a die, comprises a conductive trace comprising at least a first conductive path for allowing current in a first direction, and a second adjacent conductive path for allowing current in a second direction opposite to the first direction. Both adjacent conductive paths form at least one loop surrounding a semiconductor device on a die. The arrangement of the trace is adapted to provide compensation of EM interferences. The trace comprises two terminals being connectable to a detection circuit for detecting damages by generating a fault signal upon detection of disruption of the conductive trace due to a damage. The conductive trace comprises high resistance portions with a resistance of at least 1 kΩ, adapted for reducing self-resonance.
1. A method of monitoring edge integrity of a semiconductor die comprising a semiconductor device, the method comprising the steps of:
introducing a test signal in a conductive trace through a first conductive path surrounding a die edge,
monitoring a return test signal through a second conductive path surrounding the die edge and electrically connected to the first conductive path via an extremity, and comparing the returned signal with a reference signal, and
generating a fault signal if the output of the comparison exceeds a predetermined threshold;
wherein said introducing the test signal in the conductive trace comprises introducing the test signal in the conductive trace further comprising high resistance portions with a resistance of at least 1 kΩ adapted for reducing self-resonance; and
wherein the conductive trace further comprises polysilicon.
2. The method according to claim 1 , further comprising introducing the output of the comparison in a debouncing unit.
3. The method according to claim 1 , wherein introducing the test signal comprises introducing a test current, monitoring the return test signal comprises monitoring the voltage drop in the conductive trace, and comparing the return signal with a reference signal comprises comparing the voltage drop with a reference voltage Vth.
4. The method according to claim 1 , wherein introducing the test signal comprises applying a test voltage, monitoring the return test signal comprises measuring a reply current in the conductive trace, and comparing the return test signal with a reference signal comprises comparing the reply current with a reference current.