Method and apparatus for video coding

1. A method for video decoding in a decoder, comprising:

decoding prediction information of a current block in a current picture from a coded video bitstream, the prediction information being indicative of an inter prediction mode;

determining, for each of a plurality of sub-blocks of the current block, a usage of a first (decoder-side motion vector derivation) DMVD process on the respective sub-block of the current block at least partially based on whether a second DMVD process is determined to be used on the respective sub-block of the current block;

enabling the first DMVD process on a first sub-block of the plurality of sub-blocks of the current block;

disabling the first DMVD process on a second sub-block of the plurality of sub-blocks of the current block;

padding the second sub-block of the plurality of sub-blocks that is disabled for the first DMVD process during a gradient calculation using the first sub-block of the plurality of sub-blocks that is enabled for the first DMVD process; and

reconstructing the plurality of sub-blocks of the current block according to the inter prediction mode with the first DMVD process based on the determination for each of the plurality of sub-blocks,

wherein the second sub-block neighbors the first sub-block.

2. The method of claim 1 , wherein the first DMVD process is decoder side motion vector refinement (DMVR), and the second DMVD process is bi-directional optical flow (BDOF).

3. The method of claim 1 , wherein the first DMVD process is bi-directional optical flow (BDOF), and the second DMVD process is decoder side motion vector refinement (DMVR).

4. The method of claim 3 , wherein the DMVR is regarded as disabled when the inter prediction mode is one of a triangle merge mode, an affine mode, a generalized bi-prediction (GBi) mode, a weighted prediction mode.

5. The method of claim 3 , further comprising:

checking enable/disable status of DMVR on the plurality of sub-blocks of the current block; and

enabling/disabling DMVR for the current block based on the status of DMVR on the plurality of sub-blocks.

6. The method of claim 3 , further comprising:

enabling BDOF on a first subset of the plurality of sub-blocks of the current block; and

disabling BDOF on a second subset of the plurality of sub-blocks of the current block.

7. The method of claim 6 , wherein the padding comprises:

padding the second sub-block of the plurality of sub-blocks that is disabled for BDOF during a BDOF gradient calculation from the first sub-block of the plurality of sub-blocks that is enabled for BDOF.

8. The method of claim 1 , further comprising:

determining the usage of the first DMVD process on the respective sub-block of the current block when the second DMVD process is disabled for the respective sub-block of the current block.

9. The method of claim 1 , further comprising:

determining, when the second DMVD process is enabled, whether the second DMVD process is activated; and

disabling the first DMVD process when the second DMVD process is activated.

10. The method of claim 1 , further comprising:

determining the usage of the first DMVD process when an early skip condition is true for the second DMVD process.

11. An apparatus for video decoding, comprising:

processing circuitry configured to:

decode prediction information of a current block in a current picture from a coded video bitstream, the prediction information being indicative of an inter prediction mode;

determine, for each of a plurality of sub-blocks of the current block, a usage of a first (decoder-side motion vector derivation) DMVD process on the respective sub-block of the current block at least partially based on whether a second DMVD process is determined to be used on the respective sub-block of the current block;

enable the first DMVD process on a first sub-block of the plurality of sub-blocks of the current block;

disable the first DMVD process on a second sub-block of the plurality of sub-blocks of the current block;

pad the second sub-block of the plurality of sub-blocks that is disabled for the first DMVD process during a gradient calculation using the first sub-block of the plurality of sub-blocks that is enabled for the first DMVD process; and

reconstruct the plurality of sub-blocks of the current block according to the inter prediction mode with the first DMVD process based on the determination for each of the plurality of sub-blocks,

wherein the second sub-block neighbors the first sub-block.

12. The apparatus of claim 11 , wherein the first DMVD process is decoder side motion vector refinement (DMVR), and the second DMVD process is bi-directional optical flow (BDOF).

13. The apparatus of claim 11 , wherein the first DMVD process is bi-directional optical flow (BDOF), and the second DMVD process is decoder side motion vector refinement (DMVR).

14. The apparatus of claim 13 , wherein the DMVR is regarded as disabled when the inter prediction mode is one of a triangle merge mode, an affine mode, a generalized bi-prediction (GBi) mode, a weighted prediction mode.

15. The apparatus of claim 13 , wherein the processing circuitry is configured to:

check enable/disable status of DMVR on the plurality of sub-blocks of the current block; and

enable/disable DMVR for the current block based on the status of DMVR on the plurality of sub-blocks.

16. The apparatus of claim 13 , wherein the processing circuitry is configured to:

enable BDOF on a first subset of the plurality of sub-blocks of the current block; and

disable BDOF on a second subset of the plurality of sub-blocks of the current block.

17. The apparatus of claim 16 , wherein

the gradient calculation is a BDOF gradient calculation, and

the processing circuitry is configured to pad the second sub-block of the plurality of sub-blocks that is disabled for BDOF during the BDOF gradient calculation from the first sub-block of the plurality of sub-blocks that is enabled for BDOF.

18. The apparatus of claim 11 , wherein the processing circuitry is configured to:

determine the usage of the first DMVD process on the respective sub-block of the current block when the second DMVD process is disabled for the respective sub-block of the current block.

19. The apparatus of claim 11 , wherein the processing circuitry is configured to:

determine, when the second DMVD process is enabled, whether the second DMVD process is activated; and

disable the first DMVD process when the second DMVD process is activated.

20. The apparatus of claim 11 , wherein the processing circuitry is configured to:

determine the usage of the first DMVD process when an early skip condition is true for the second DMVD process.