IP Library Granted Patent US 10,937,497
Granted Patent B2
US 10,937,497 · App. 16/735,643 · Granted Mar 2, 2021

Methods for accessing 1-R resistive change element arrays

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Quick Facts
Patent No.
US 10,937,497
App. No.
16/735,643
Granted
Mar 2, 2021
Kind
B2
Abstract

Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

Claims (24)

1. A method for determining the resistive state of a resistive change element within a resistive change element array, comprising:

providing a resistive change element array, said resistive change element array comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line;

a least one resistive reference element, said resistive reference element having a first terminal in electrical communication with a word line and a second terminal in electrical communication with a bit line;

selecting one of said plurality of word lines and one of said plurality of bit lines, said selected word line and selected bit line corresponding to selected resistive change element;

initializing all of said bit lines and all of said word lines within said resistive change element array to a ground;

charging said selected word line to a preselected voltage while holding all other word lines at ground and allowing all bit lines to float;

measuring the voltage on said selected bit line and storing said voltage as a first measured value;

re-initializing all of said bit lines and all of said word lines within said resistive change element array to a ground;

selecting one resistive reference element, said selected resistive reference element in electrical communication with said selected bit line, and charging the word line in electrical communication with said at least one selected resistive reference element to a preselected voltage while holding all other word lines at ground and allowing all bit lines to float;

measuring the voltage on said selected bit line and storing said voltage as a second measured value;

comparing said first measured value with said second measured value to determine the resistive state of said selected resistive change element.

2. The method of claim 1 wherein said resistive change element array further comprises a plurality of measurement and storage elements, each of said measurement and storage elements responsive to one of said plurality of bit lines.

3. The method of claim 2 wherein said plurality of measurement and storage elements are capable of measuring and storing two voltages in successive operations, comparing said stored voltages, and outputting a logic value corresponding to said comparison.

4. The method of claim 1 wherein said first measured value corresponds to a voltage divide between said selected resistive change element and the parallel combination of all unselected resistive change elements and resistive reference elements in electrical communication with said selected bit line and said second measured value corresponds to a voltage divide between said selected resistive reference element and the parallel combination of all resistive change elements in electrical communication with said selected bit line.

5. The method of claim 4 wherein said first measured value and said second measured value are functions of the resistive states stored in the unselected cells in electrical communication with said selected bit line.

6. The method of claim 1 wherein a first logic value corresponds to said first measured value being higher than said second measured value and a second logic value corresponds to said first measured value being lower than said second measured value.

7. The method of claim 1 wherein said resistive change elements are two-terminal nanotube switching elements.

8. The method of claim 7 wherein said two-terminal nanotube switching elements comprise a nanotube fabric.

9. The method of claim 1 wherein said resistive change elements are metal oxide memory elements.

10. The method of claim 1 wherein said resistive change elements are phase change memory elements.

11. The method of claim 1 wherein said resistive change element array is a memory array.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056790/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2020
From: BERTIN, CLAUDE L.; CLEVELAND, LEE
To: NANTERO, INC.
Reel/Frame 053889/0405 →