THREE-DIMENSIONAL MEMORY DEVICE WITH VIA STRUCTURES SURROUNDED BY PERFORATED DIELECTRIC MOAT STRUCTURE AND METHODS OF MAKING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.
1 . A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers;
a perforated dielectric moat structure vertically extending through the alternating stack and including a plurality of lateral openings at each level of the insulating layers and not including any opening at levels of the electrically conductive layers; and
an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack.
2 . The three-dimensional memory device of claim 1 , wherein:
the perforated dielectric moat structure comprises a row of dielectric pillar portions at each level of the insulating layers; and
each of the insulating layers laterally extends between neighboring pairs of dielectric pillar portions from outside the perforated dielectric moat structure to inside the perforated dielectric moat structure.
3 . The three-dimensional memory device of claim 2 , wherein each row of dielectric pillar portions is arranged along a periphery of the perforated dielectric moat structure at a level of one of the insulating layers.
4 . The three-dimensional memory device of claim 2 , wherein the rows of dielectric pillar portions located at different levels of the insulating layers have an areal overlap between them.
5 . The three-dimensional memory device of claim 2 , wherein the perforated dielectric moat structure comprises an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate.
6 . The three-dimensional memory device of claim 5 , wherein:
the dielectric material plates comprise a different material than the insulating layers; and
the interconnection via structure vertically extends through a vertical stack of dielectric material plates and the insulating layers in an area surrounded by the perforated dielectric moat structure.
7 . The three-dimensional memory device of claim 6 , wherein:
the insulating layers comprise a silicon oxide material; and
the dielectric material plates comprise silicon nitride.
8 . The three-dimensional memory device of claim 5 , wherein each of the dielectric material plates has a respective uniform thickness throughout, and contacts a planar bottom surface of a respective overlying one of the insulating layers and contacts a planar top surface of a respective underlying one of the insulating layers.
9 . The three-dimensional memory device of claim 5 , wherein each of the annular dielectric plate portions comprises:
a continuous inner sidewall including a plurality of laterally-convex and vertically-planar inner sidewall segments that are adjoined among one another; and
a continuous outer sidewall including a plurality of laterally-convex and vertically-planar outer sidewall segments that are adjoined to each other.
10 . The three-dimensional memory device of claim 9 , wherein each of the continuous inner sidewalls and the continuous outer sidewalls is laterally offset from a respective overlying row of dielectric pillar portions by a uniform lateral offset distance.
11 . The three-dimensional memory device of claim 1 , further comprising:
lower-level dielectric material layers disposed between the substrate and the alternating stack; and
lower-level metal interconnect structures embedded within the lower-level dielectric material layers, wherein the interconnection via structure contacts a top surface of one of the lower-level metal interconnect structures.
12 . The three-dimensional memory device of claim 11 , further comprising field effect transistors located over the substrate and including a node that is electrically connected to the interconnection via structure through a subset of the lower-level metal interconnect structures.
13 . The three-dimensional memory device of claim 11 , further comprising:
upper-level dielectric material layers located above the alternating stack; and
upper-level metal interconnect structures embedded within the upper-level dielectric material layers, wherein the interconnection via structure contacts a bottom surface of one of the upper-level metal interconnect structures.
14 . The three-dimensional memory device of claim 1 , wherein the vertical stack of memory elements comprises portions of a charge storage layer located at each level of the electrically conductive layers and laterally spaced from a respective one of the vertical semiconductor channels by a tunneling dielectric layer.
15 . A method for forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein the sacrificial material layers comprise a dielectric material;
forming a row of moat region openings through the alternating stack, wherein the row of moat region openings is arranged in a pattern that surrounds an area within the alternating stack;
forming a moat trench by laterally expanding each moat region opening within the row of moat region openings at levels of the sacrificial material layers, wherein the moat trench comprises a continuously extending volume that laterally surrounds a patterned portion of a respective sacrificial material layer at each level of the sacrificial material layers;
forming a perforated dielectric moat structure vertically extending through the alternating stack by filling the moat trench with a dielectric fill material; and
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers.
16 . The method of claim 15 , further comprising forming an interconnection via structure laterally surrounded by the perforated dielectric moat structure.
17 . The method of claim 16 , wherein each moat region opening within the row of moat region openings is laterally expanded at levels of the sacrificial material layers by performing an isotropic etch process that etches a material of the sacrificial material layers selective to a material of the insulating layers.
18 . The method of claim 17 , wherein:
remaining portions of the sacrificial material layers after the isotropic etch process comprise a vertical stack of dielectric material plates that is laterally surrounded by the moat trench; and
the interconnection via structure vertically extends through each insulating layer within the alternating stack and through the vertical stack of dielectric material plates.
19 . The method of claim 18 , wherein:
the perforated dielectric moat structure comprises annular dielectric plate portions that are formed at levels of the sacrificial material layers; and
each of the annular dielectric plate portions comprises:
a continuous inner sidewall including a plurality of laterally-convex and vertically-planar inner sidewall segments that are adjoined among one another, and
a continuous outer sidewall including a plurality of laterally-convex and vertically-planar outer sidewall segments that are adjoined among one another.
20 . The method of claim 15 , further comprising forming lower-level metal interconnect structures embedded within lower-level dielectric material layers over the substrate, wherein:
the alternating stack is subsequently formed over the lower-level dielectric material layers; and
the interconnection via structure is formed on a top surface of one of the lower-level metal interconnect structures.