Power semiconductor module with dimples in metallization layer below foot of terminal

1. A power semiconductor module, comprising:

an insulating substrate with a top metallization layer;

a semiconductor chip bonded to the top metallization layer; and

a terminal connected with a foot to the top metallization layer and electrically interconnected to the semiconductor chip;

wherein at least one of the top metallization layer and a bottom metallization layer of the insulating substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below the foot;

wherein at least one dimple is located outside an edge of the foot;

wherein the foot of the terminal is welded to the top metallization layer in the connection region; and

wherein the connection region protrudes out of under the foot at least ¼ of a maximal diameter of the foot and wherein the one or more dimples distributed outside of an edge of the foot have a maximal distance from the edge of the foot of less than ¼ of a maximal diameter of the foot.

2. The power semiconductor module of claim 1 , wherein the dimples are distributed below the foot.

3. The power semiconductor module of claim 1 , wherein all of the dimples are distributed below the foot.

4. The power semiconductor module of claim 1 , wherein the dimples have a depth smaller than a thickness of an associated metallization layer or layers, the associated metallization layer or layers being the top metallization layer and/or the bottom metallization layer that comprises the plurality of dimples.

5. The power semiconductor module of claim 1 , wherein the dimples reach through an associated metallization layer or layers, the associated metallization layer or layers being the top metallization layer and/or the bottom metallization layer that comprises the plurality of dimples.

6. The power semiconductor module of one claim 1 , wherein neighboring dimples have a distance with respect to each other of less than three diameters of the dimples.

7. The power semiconductor module of one claim 1 , wherein the dimples are distributed in a regular pattern.

8. The power semiconductor module of claim 1 , wherein the at least one dimple comprises a plurality of dimples distributed along an edge of the foot on at least three sides of the foot.

9. The power semiconductor module of claim 1 , wherein the insulating substrate comprises a ceramics layer made of at least one of aluminum nitride, aluminum oxide, and silicon nitride.

10. The power semiconductor module of claim 9 , further comprising a base plate to which the insulating substrate is bonded with the bottom metallization layer, wherein one or more dimples are distributed in the bottom metallization layer between the ceramics layer and the base plate.

11. The power semiconductor module of claim 8 , wherein all of the dimples of the at least one dimple are distributed only along the three sides of the foot.

12. The power semiconductor module of claim 8 , wherein the dimples of the at least one dimple are distributed in an array beneath the foot.

13. A method of manufacturing a power semiconductor module, the method comprising:

providing an insulating substrate;

forming a plurality of dimples in at least one of a top metallization layer and a bottom metallization layer of the insulating substrate, wherein the dimples are formed in a connection region for a terminal of the power semiconductor module;

bonding a semiconductor chip to the top metallization layer; and

welding a foot of the terminal to the top metallization layer in the connection region, wherein at least one dimple comprises a plurality of dimples distributed along an edge of the foot only along three sides of the foot.

14. The method of claim 13 , wherein the dimples are formed by etching the at least one of the top metallization layer and the bottom metallization layer.

15. The method of claim 13 , wherein the foot of the terminal is at least one of friction welded and ultrasonically welded to the top metallization layer.

16. The method of claim 13 , wherein the dimples have a depth smaller than a thickness of an associated metallization layer or layers, the associated metallization layer or layers being the top metallization layer and/or the bottom metallization layer that comprises the plurality of dimples.

17. The method of claim 13 , wherein the insulating substrate comprises a ceramics layer made of at least one of aluminum nitride, aluminum oxide, and silicon nitride.

18. A power semiconductor device, comprising:

an insulating substrate with a top metallization layer;

a semiconductor chip bonded to the top metallization layer; and

a terminal connected with a foot to the top metallization layer and electrically interconnected to the semiconductor chip;

wherein at least one of the top metallization layer and a bottom metallization layer of the insulating substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below the foot;

wherein the foot of the terminal is welded to the top metallization layer in the connection region;

wherein the connection region protrudes out of under the foot at least ¼ of a maximal diameter of the foot; and

wherein dimples outside of an edge of the foot have a maximal distance from the edge of the foot of less than ¼ of a maximal diameter of the foot.

19. The power semiconductor device of claim 18 , wherein all of the dimples are outside of the edge of the foot.

20. The power semiconductor device of claim 18 , wherein a first group of the dimples are outside of the edge of the foot and a second group of the dimples are inside of the edge of the foot, the second group of dimples being distributed along edges of the foot.

21. The power semiconductor device of claim 18 , wherein a first group of the dimples are outside of the edge of the foot and a second group of the dimples are inside of the edge of the foot, the second group of dimples being distributed in an array beneath the foot.