Devices and methods of vertical integrations of semiconductor chips, magnetic chips, and lead frames
View Patent ↗Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.
1. An integrated circuit (IC) device, comprising:
a multi-layer IC structure including a first layer and a second layer,
wherein the first layer includes a magnetic chip, the magnetic chip including a first terminal and a second terminal, and
wherein the second layer includes a first semiconductor chip, the first semiconductor chip including a terminal on a surface thereof facing the magnetic chip; and
a lead frame including a first lead and a bonding pad,
wherein the magnetic chip in the first layer is vertically bonded to the bonding pad of the lead frame,
wherein the first semiconductor chip in the second layer is vertically bonded to the magnetic chip in the first layer,
wherein the terminal on the surface of the first semiconductor chip facing the magnetic chip is connected to the first terminal of the magnetic chip, the magnetic chip in the first layer being disposed between the bonding pad of the lead frame and the first semiconductor chip in the second layer,
wherein the second terminal of the magnetic chip is connected to the first lead of the lead frame, and
wherein the multi-layer IC structure and the bonding pad of the lead frame are encapsulated within a protective enclosure.
2. The IC device of claim 1 wherein the magnetic chip includes organic material, one or more copper conductor layers, and one or more magnetic material layers, and wherein the organic material of the magnetic chip is one or more of bonded and laminated with the one or more copper conductor layers and the one or more magnetic material layers.
3. The IC device of claim 2 wherein the organic material of the magnetic chip includes one or more of epoxy, polyimide, epoxy mixed with polyimide, and liquid crystal polymer.
4. The IC device of claim 3 wherein the one or more magnetic material layers include one or more of a magnetic metal alloy and a sintered ferrite material.
5. The IC device of claim 4 wherein the one or more magnetic material layers include one or more magnetic composite materials, and wherein the one or more magnetic composite materials include one or more of Fe, FeNi, FeSiAl, FeSiAlCr, Co, MnZn, NiZn, and NiZnCu.
6. The IC device of claim 1 wherein the protective enclosure is made of a molding compound.
7. The IC device of claim 1 wherein the magnetic chip in the first layer is configured as one or more of a single inductor, multiple inductors, coupled inductors with multiple coil windings, and a transformer having a primary winding and a secondary winding.
8. The IC device of claim 1 wherein the magnetic chip further includes a third terminal, wherein the lead frame further includes a second lead, wherein the second layer further includes a second semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip in the second layer includes a first terminal on a surface thereof facing away from the magnetic chip in the first layer, wherein the first terminal on the surface of the first semiconductor chip facing away from the magnetic chip is connected to the third terminal of the magnetic chip, and wherein the first terminal on the surface of the second semiconductor chip facing away from the magnetic chip is connected to the second lead of the lead frame.
9. The IC device of claim 8 wherein each of the first semiconductor chip and the second semiconductor chip has a second terminal on the surface thereof facing away from the magnetic chip, and wherein the second terminal on the surface of the first semiconductor chip facing away from the magnetic chip is connected to the second terminal on the surface of the second semiconductor chip facing away from the magnetic chip.