Selector transistor with continuously variable current drive
A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.
1. A memory cell structure including a selector transistor having a three-dimensional transistor structure coupled to a memory element, the memory cell structure comprising:
a two-terminal resistive memory element having a first electrode and a second electrode, wherein an electrical current flowing between the first electrode to the second electrode switches the memory state of the memory element;
the selector transistor having a first electrode coupled to the first electrode of the memory element, a second electrode coupled to receive a source-line voltage and a control terminal coupled to receive a gate voltage, wherein the selector transistor comprises:
a semiconductor substrate having a surface;
a semiconductor pillar structure formed on the semiconductor substrate and being integral to the selector transistor, the semiconductor pillar having a first dimension parallel with the surface of the semiconductor substrate and a second dimension parallel with the semiconductor substrate and perpendicular to the first dimension, wherein the first and second dimensions are unequal with one another, wherein the semiconductor pillar structure includes a first doped region forming the first electrode and a second doped region forming the second electrode of the selector transistor;
a gate dielectric layer surrounding the semiconductor pillar structure; and
an electrically conductive gate structure surrounding the semiconductor pillar structure and the gate dielectric layer and forming the control terminal of the selector transistor,
wherein the selector transistor provides a drive current flowing between the first and second electrodes of the selector transistor as a function of the gate voltage received at the control terminal, the drive current having a magnitude being a function of the larger of the first or second dimension of the semiconductor pillar structure of the selector transistor, the drive current being provided to the memory element as the electrical current to switch the memory state of the memory element.
2. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure is formed by selective epitaxial growth on the semiconductor substrate.
3. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure is substantially mono-crystalline.
4. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure is at least 80 percent monocrystalline by volume.
5. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure is at least 90 percent monocrystalline by volume.
6. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is rectangular.
7. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is oval.
8. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is elliptical.
9. The memory cell structure as in claim 1 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is an elongated polygon.
10. A memory device, comprising:
a selector transistor having a first electrode, a second electrode and a control terminal, the second electrode being coupled to receive a source-line voltage and the control terminal being coupled to receive a gate voltage, wherein the selector transistor comprises:
a semiconductor substrate having a surface;
a semiconductor pillar structure formed on the semiconductor substrate and being integral to the selector transistor, the semiconductor pillar having a first dimension parallel with the surface of the semiconductor substrate and a second dimension parallel with the semiconductor substrate and perpendicular to the first dimension, wherein the first and second dimensions are unequal with one another, wherein the semiconductor pillar structure includes a first doped region forming the first electrode and a second doped region forming the second electrode;
a gate dielectric layer surrounding the semiconductor pillar structure;
an electrically conductive gate structure surrounding the semiconductor pillar structure and the gate dielectric layer and forming the control terminal; and
a magnetic tunnel junction (MTJ) memory element having a first electrode and a second electrode, the first electrode being electrically connected to the first electrode of the semiconductor pillar structure of the selector transistor, wherein the selector transistor provides a drive current flowing between the first and second electrodes of the selector transistor as a function of the gate voltage received at the control terminal, the drive current having a magnitude being a function of the larger of the first or second dimension of the semiconductor pillar structure of the selector transistor, the drive current being provided to the MTJ memory element as a drive current to switch a magnetic orientation of a magnetic free layer of the MTJ memory element.
11. The memory device as in claim 10 , further comprising an electrically conductive electrode disposed between and electrically connecting the first electrode of the MTJ memory element and the first electrode of the semiconductor pillar structure.
12. The memory device as in claim 10 , wherein the semiconductor pillar structure is epitaxially grown on the surface of the semiconductor substrate.
13. The memory device as in claim 10 , wherein the semiconductor pillar structure is substantially mono-crystalline.
14. The memory device as in claim 10 , wherein the semiconductor pillar structure is at least 80 percent monocrystalline by volume.
15. The memory device as in claim 10 , wherein the semiconductor pillar structure is at least 90 percent monocrystalline by volume.
16. The memory device as in claim 10 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is rectangular.
17. The memory device as in claim 10 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is oval.
18. The memory device as in claim 10 , wherein the semiconductor pillar structure has a cross-section parallel with the semiconductor substrate that is an elongated polygon.
19. The memory cell structure as in claim 1 , wherein the memory element comprises one of a magnetic tunnel junction (MTJ) memory element, an ReRAM; a Correlated Electron RAM (CERAM), a Conductive Bridge RAM (CBRAM), a memristor structure, or a Phase Change Material (PCM).