Steep slope transistors with threshold switching devices
A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.
1. A field effect transistor (FET) comprising:
a source region and a drain region; and
a threshold switching device in direct contact with the source region or the drain region,
wherein the FET has a subthreshold swing of about 5 mV/dec with a transition range of over 10 5 in both sweep directions at room temperature.
2. The FET of claim 1 , wherein the FET is an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT).
3. The FET of claim 1 , wherein the threshold switching device has a metal-insulator-metal (MIM) structure comprising:
a first electrode;
a second electrode; and
a threshold switching layer between the first electrode and the second electrode.
4. The FET of claim 3 , wherein the first electrode comprises titanium.
5. The FET of claim 4 , wherein the first electrode is in direct contact with the source region or the drain region.
6. The FET of claim 4 , wherein the abrupt transition results in a steep threshold slope.
7. The FET of claim 3 , wherein the second electrode comprises silver.
8. The FET of claim 3 , wherein the threshold switching layer comprises SiO 2 .
9. The FET of claim 1 , wherein an abrupt transition from a high resistance state to a low resistance state occurs when an applied voltage reaches a threshold value.
10. The FET of claim 1 , wherein the FET comprises Si, Ge, SiGe, or a binary or ternary compound semiconductor comprising elements from Groups II-VI, III-V, and IV-IV and Group III nitrides.
11. The FET of claim 1 , wherein the FET has a leakage current of 10 −5 μA/μm or less.
12. The FET of claim 1 , wherein the FET has an on-to-off current ratio (I ON /I OFF ) of greater than 10 7 .
13. The FET of claim 1 , wherein the FET comprises:
a silicon substrate;
a GaN buffer layer on the Si substrate;
a GaN channel layer on the GaN buffer layer;
an AlN interlayer;
a barrier layer comprising Al, Ga, and N; and
a GaN cap layer.
14. A method of fabricating the field effect transistor (FET) of claim 1 , the method comprising:
depositing a first electrode layer directly on the source region or the drain region;
depositing a threshold switching layer directly on the first electrode layer to yield the threshold switching device; and
depositing a second electrode layer directly on the threshold switching layer to yield the FET.
15. The method of claim 14 , wherein the first electrode layer comprises titanium.
16. The method of claim 14 , wherein the second electrode layer comprises silver.
17. The method of claim 14 , wherein the threshold switching layer comprises SiO 2 .