Bonded three-dimensional memory devices having bonding layers
Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
a plurality of first NAND memory strings;
a plurality of first bit lines (BLs), at least one of the first BLs being conductively connected to a respective one of the first NAND memory strings;
a plurality of first conductor layers, and
a first bonding layer comprising a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers;
a second semiconductor structure comprising:
a plurality of second NAND memory strings;
a plurality of second BLs, at least one of the second BLs being conductively connected to a respective one of the second NAND memory strings;
a plurality of second conductor layers, and
a second bonding layer comprising a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs and a plurality of second word line bonding contacts conductively connected to the second conductor layers; and
a bonding interface between the first bonding layer and the second bonding layer, wherein at the bonding interface, the first bit line bonding contacts are conductively connected to the second bit line bonding contacts and the first word line bonding contacts are conductively connected to the second word line bonding contacts, wherein
the plurality of first bit line bonding contacts and the plurality of second bit line bonding contacts are routed to and bonded at a first bonding region that is laterally away from the first and second BLs; and
the plurality of first word line bonding contacts and the plurality of second word line bonding contacts are routed to and bonded at a second bonding region that is laterally away from the first and second conductor layers.
2. The 3D memory device of claim 1 , wherein at least one of the first NAND memory strings is conductively connected to at least one of the second NAND memory strings through bonded first and second bit line bonding contacts, and at least one of the first conductor layers are conductively connected to at least one of the second conductor layers through bonded first and second word line bonding contacts.
3. The 3D memory device of claim 2 , wherein:
the first semiconductor structure comprises:
the first bonding layer at the bonding interface, and
the first BLs under the first bonding layer; and
the second semiconductor structure comprises:
the second bonding layer at the bonding interface, and
the second BLs above the second bonding layer.
4. The 3D memory device of claim 3 , wherein
the first semiconductor structure further comprises:
a first memory stack under the first bonding layer, the first memory stack comprising interleaved the plurality of first conductor layers and a plurality of first insulating layers, and
the plurality of first NAND memory strings extending vertically through the first memory stack; and
the second semiconductor structure further comprises:
a second memory stack above the second bonding layer, the second memory stack comprising interleaved the plurality of second conductor layers and a plurality of second insulating layers, and
the plurality of second NAND memory strings extending vertically through the second memory stack.
5. The 3D memory device of claim 1 , wherein:
the first semiconductor structure comprises a first interconnect layer comprising a plurality of first conductive routings between the plurality of first NAND memory strings and the first bonding layer;
the second semiconductor structure comprises a second interconnect layer comprising a plurality of second conductive routings between the plurality of second NAND memory strings and the second bonding layer; and
the first BLs and the first conductor layers are conductively connected to and routed by the first conductive routing to the first bit line bonding contacts and the first word line bonding contacts at respective bonding regions, and the second BLs and the second conductor layers are conductively connected to and routed by the second conductive routing to the second bit line bonding contacts and the second word line bonding contacts at the respective bonding regions.
6. The 3D memory device of claim 1 , wherein:
the plurality of first BLs and second BLs are vertically arranged in a staggered manner;
the first memory stack and the second memory stack are vertically arranged in a staggered manner;
each of the first and the second BLs is conductively connected to the respective bit line bonding contact through a respective via structure and the respective conductive routings; and
each of the first and second conductor layers is conductively connected to a respective word line bonding contact through another respective via structure and the respective conductive routings.
7. The 3D memory device of claim 6 , further comprising:
a third semiconductor structure above the second semiconductor structure, the third semiconductor structure comprising a peripheral circuit of the first and second memory stacks; and
a second bonding interface between the second semiconductor structure and a third bonding layer of the third semiconductor structure.
8. The 3D memory device of claim 7 , wherein:
the second semiconductor structure comprises a semiconductor layer above and in contact with the second NAND memory strings;
the first semiconductor structure comprises a substrate under and in contact with the first NAND memory strings; and
the third semiconductor structure comprises
a third interconnect layer between the third bonding layer and the peripheral circuit,
the peripheral circuit above and in contact with the third interconnect layer,
a second semiconductor layer above and in contact with the peripheral circuit, and
a pad-out interconnect layer above the second semiconductor layer.
9. A three-dimensional (3D) memory device, comprising:
a stack structure comprising a plurality of pairs of bonded semiconductor structures, wherein each of the pairs comprises:
a first semiconductor structure comprising a plurality of first NAND memory strings, a plurality of first bit lines (BLs) conductively connected to respective first NAND memory strings, a plurality of first conductor layers, and a first bonding layer comprising a plurality of first bit line bonding contacts conductively connected to the first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers, respectively;
a second semiconductor structure comprising a plurality of second NAND memory strings, a plurality of second BLs conductively connected to respective second NAND memory strings, a plurality of second conductor layers, and a second bonding layer comprising a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs and a plurality of second word line bonding contacts conductively connected to the second conductor layers, respectively; and
a bonding interface between the first bonding layer and the second bonding layer, wherein, at the bonding interface, the first bit line bonding contacts are in contact with the second bit line bonding contacts and the first word line bonding contacts are in contact with the second word line bonding contacts, respectively, and
a third semiconductor structure bonded to and conductively connected to the stack structure, wherein the third semiconductor structure comprises a peripheral circuit of at least one pair of bonded semiconductor structures, wherein
the plurality of first bit line bonding contacts and the plurality of second bit line bonding contacts are routed to and bonded at a first bonding region that is laterally away from the first and second BLs; and
the plurality of first word line bonding contacts and the plurality of second word line bonding contacts are routed to and bonded at a second bonding region that is laterally away from the first and second conductor layers.
10. The 3D memory device of claim 9 , wherein
at least one of the first NAND memory strings is conductively connected to at least one of the second NAND memory strings through the bonded first and second bit line bonding contacts; and
at least one of the first conductor layers is conductively connected to at least one of the second conductor layers through the bonded first and second word line bonding contacts.
11. The 3D memory device of claim 10 , wherein
the first semiconductor structure comprises:
the first bonding layer at the bonding interface,
the first BLs under the first bonding layer,
a first memory stack under the first bonding layer, the first memory stack comprising interleaved the plurality of first conductor layers and a plurality of first insulating layers, and
the plurality of first NAND memory strings extending vertically through the first memory stack; and
the second semiconductor structure comprises:
the second bonding layer at the bonding interface,
the second BLs above the second bonding layer,
a second memory stack above the second bonding layer, the second memory stack comprising interleaved the plurality of second conductor layers and a plurality of second insulating layers, and
the plurality of second NAND memory strings extending vertically through the second memory stack.
12. The 3D memory device of claim 9 , wherein:
the first semiconductor structure comprises a first interconnect layer comprising a plurality of first conductive routings between the plurality of first NAND memory strings and the first bonding layer;
the second semiconductor structure comprises a second interconnect layer comprising a plurality of second conductive routings between the plurality of second NAND memory strings and the second bonding layer; and
the first BLs and the first conductor layers are conductively connected to and routed by the first conductive routing to the first bit line bonding contacts and the first word line bonding contacts at respective bonding regions, and the second BLs and the second conductor layers are conductively connected to and routed by the second conductive routing to the second bit line bonding contacts and the second word line bonding contacts at the respective bonding regions.
13. The 3D memory device of claim 9 , wherein
the first BLs and second BLs are vertically arranged in a staggered manner;
the first memory stack and the second memory stack are vertically arranged in a staggered manner;
each of the first and the second BLs is conductively connected to the respective bit line bonding contact through a respective via structure and the respective conductive routings; and
each of the first and second conductor layers is conductively connected to the respective word line bonding contact through another respective via structure and the respective conductive routings.
14. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
a first memory stack comprising a plurality of first conductor layers;
a plurality of first bit lines (BLs), at least one of the first BLs being conductively connected to the first memory stack; and
a first bonding layer comprising a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers;
a second semiconductor structure comprising:
a second memory stack comprising a plurality of second conductor layers;
a plurality of second BLs, at least one of the second BLs being conductively connected to the second memory stack; and
a second bonding layer comprising a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs and a plurality of second word line bonding contacts conductively connected to the second conductor layers; and
a bonding interface between the first bonding layer and the second bonding layer, wherein, at the bonding interface, the first bit line bonding contacts are in contact with the second bit line bonding contacts, and the first word line bonding contacts are in contact with the second word line bonding contacts, wherein:
the plurality of first bit line bonding contacts and the plurality of second bit line bonding contacts are routed to and bonded at a first bonding region that is laterally away from the first and second BLs; and
the plurality of first word line bonding contacts and the plurality of second word line bonding contacts are routed to and bonded at a second bonding region that is laterally away from the first and second conductor layers.
15. The 3D memory device of claim 14 , wherein
the first memory stack comprises at least one first NAND memory string and the second memory stack comprises at least one second NAND memory string, the at least one first NAND memory string being conductively connected to the at least one of the second NAND memory string through bonded first and second bit line bonding contacts; and
at least one of the first conductor layers is conductively connected to at least one of the second conductor layers through bonded first and second word line bonding contacts.
16. The 3D memory device of claim 15 , wherein:
the first semiconductor structure comprises:
the first bonding layer at the bonding interface, and
the first BLs under the first bonding layer; and
the second semiconductor structure comprises:
the second bonding layer at the bonding interface, and
the second BLs above the second bonding layer.
17. The 3D memory device of claim 14 , wherein:
the plurality of first BLs and second BLs are vertically arranged in a staggered manner in a vertical direction.
18. The 3D memory device of claim 14 , wherein:
the first memory stack and the second memory stack are vertically arranged in a staggered manner.
19. The 3D memory device of claim 14 , wherein:
each of the first and the second BLs is conductively connected to the respective bit line bonding contact through a respective via structure and the respective conductive routings; and
each of the first and second conductor layers is conductively connected to a respective word line bonding contact through another respective via structure and the respective conductive routings.
20. The 3D memory device of claim 14 , further comprising:
a third semiconductor structure above the second semiconductor structure, the third semiconductor structure comprising a peripheral circuit of the first and second memory stacks; and
a second bonding interface between the second semiconductor structure and a third bonding layer of the third semiconductor structure.