Gate structures for semiconductor devices

1. A semiconductor device, comprising:

a substrate;

first and second stacks of first and second nanostructured layers arranged in an alternating configuration on the substrate;

first and second epitaxial regions of opposite conductivity type on the first and second stacks, respectively;

first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively; and

first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively,

wherein the first GAA structure comprises an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer, and

wherein the second GAA structure comprises an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

2. The semiconductor device of claim 1 , wherein the metal growth inhibition layer is disposed on the Al-free p-type work function metal layer.

3. The semiconductor device of claim 1 , wherein the metal growth inhibition layer is in physical contact with the Al-free p-type work function metal layer.

4. The semiconductor device of claim 1 , wherein the metal growth inhibition layer surrounds the second nanostructured channel regions.

5. The semiconductor device of claim 1 , wherein the Al-based n-type work function metal layer is in physical contact with the first gate dielectric layer.

6. The semiconductor device of claim 1 , wherein the Al-free p-type work function metal layer is in physical contact with the second gate dielectric layer.

7. The semiconductor device of claim 1 , wherein the first metal capping layer is configured to block diffusion of oxygen into the Al-based n-type work function metal layer.

8. The semiconductor device of claim 1 , further comprising a metal layer disposed between the Al-free p-type work function metal layer and the metal growth inhibition layer.

9. The semiconductor device of claim 1 , wherein the Al-based n-type work function metal layer has a work function value closer to a conduction band energy than a valence band energy of the first nanostructured channel regions.

10. The semiconductor device of claim 1 , wherein the Al-free p-type work function metal layer has a work function value closer to a valence band energy than a conduction band energy of the second nanostructured channel regions.

11. A semiconductor device, comprising:

a substrate;

first and second stacks of first and second nanostructured layers arranged in an alternating configuration on the substrate;

first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively;

a first gate structure disposed on the first nanostructured channel region, wherein the first gate structure comprises an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer; and

a second gate structure disposed on the second nanostructured channel region, wherein the second gate structure comprises an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

12. The semiconductor device of claim 11 , wherein the metal growth inhibition layer is in physical contact with the Al-free p-type work function metal layer.

13. The semiconductor device of claim 11 , wherein the metal growth inhibition layer surrounds the second nanostructured channel regions.

14. The semiconductor device of claim 1 , further comprising a metal layer disposed between the Al-free p-type work function metal layer and the metal growth inhibition layer.

15. A method of fabricating a semiconductor device, comprising:

forming first and second stacks of first and second nanostructured layers arranged in an alternating configuration on a substrate;

forming first and second nanostructured channel regions in the first and second nanostructured layers of the first and second stacks, respectively;

selectively forming an Al-free p-type work function metal layer on the first nanostructured channel regions;

selectively depositing a metal growth inhibition layer on the Al-free p-type work function metal layer;

selectively depositing an Al-based n-type work function metal layer on the second nanostructured channel regions;

depositing a metal capping layer on the Al-free p-type work function metal layer and the Al-based n-type work function metal layer; and

depositing a fluorine-free gate metal fill layer or a chlorine-free gate metal fill layer on the metal capping layer.

16. The method of claim 15 , wherein the selectively forming the Al-free p-type work function metal layer comprises:

depositing a layer of Al-free metallic material on the first and second nanostructured channel regions, wherein the Al-free metallic material has a work function value closer to a valence band energy than a conduction band energy of the second nanostructured channel regions;

selectively forming a masking layer on a first portion of the layer of Al-free metallic material on the first nanostructured channel regions; and

etching a second portion of the layer of Al-free metallic material on the second nanostructured channel regions.

17. The method of claim 15 , wherein the selectively depositing the metal growth inhibition layer comprises:

performing a first soaking process with a metal precursor on the Al-free p-type work function metal layer; and

performing a second soaking process with a silicon precursor on the Al-free p-type work function metal layer.

18. The method of claim 15 , wherein the selectively depositing the Al-based n-type work function metal layer comprises depositing a layer of Al-based metallic material on the second nanostructured channel regions, wherein the Al-based metallic material has a work function value closer to a conduction band energy than a valence band energy of the second nanostructured channel regions.

19. The method of claim 15 , wherein the selectively depositing the Al-based n-type work function metal layer comprises:

depositing a layer of metallic material on the second nanostructured channel regions; and

doping the layer of metallic material with Al dopants to form a layer of Al-based metallic material with a work function value closer to a conduction band energy than a valence band energy of the first nanostructured channel regions.

20. The method of claim 15 , wherein the selectively forming the Al-free p-type work function metal layer is performed prior to the selectively depositing the Al-based n-type work function metal layer.