Methods for VFET cell placement and cell architecture
A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1 st cell and a 2 nd cell placed next to each other in a cell width direction, wherein the 1 st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1 st cell, and connects a vertical field-effect transistor (VFET) of the 1 st cell to a power rail of the 1 st cell, wherein a 2 nd cell includes a connector connected to a power rail of the 2 nd cell, wherein the fin of the 1 st cell and the connector of the 2 nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1 st cell and the connector of the 2 nd cell are merged.
1. A cell architecture comprising a 1 st cell and a 2 nd cell placed next to each other in a cell width direction,
wherein the 1 st cell comprises an at least two-fin connector which is formed around at least two fins of the 1 st cell, and connects at least one vertical field-effect transistor (VFET) of the 1 st cell to a power rail of the 1 st cell,
wherein the 2 nd cell comprises an at least one-fin connector formed around at least one fin of the 2 nd cell to connect at least one VFET of the 2 nd cell for internal signal routing without being connected to a power rail of the 2 nd cell, and
wherein the at least two fins of the 1 st cell and the at least one fin of the 2 nd cell are placed next to each other in the cell width direction in the cell architecture.
2. The cell architecture of claim 1 , wherein the at least two-fin connector of the 1 st cell is an at least two-fin bottom S/D region of the at least one VFET of the 1 st cell, and the at least one-fin connector of the 2 nd cell is an at least one-fin bottom S/D region of the at least one VFET of the 2 nd cell.
3. The cell architecture of claim 1 , wherein the at least two-fin connector of the 1 st cell is an at least two-fin top S/D contact structure formed on at least two top S/D regions of the at least one VFET of the 1 st cell, and the at least one-fin connector of the 2 nd cell is an at least one-fin top S/D contact structure formed on at least one top S/D region of the at least one VFET of the 2 nd cell.
4. A cell architecture comprising at least a 1 st cell and a 2 nd cell placed next to each other in a cell width direction,
wherein the 1 st cell comprises a one-fin connector which is formed around a fin among a plurality of fins of the 1 st cell, and connects a vertical field-effect transistor (VFET) of the 1 st cell to a power rail of the 1 st cell,
wherein a 2 nd cell comprises a connector connected to a power rail of the 2 nd cell,
wherein the fin of the 1 st cell and the connector of the 2 nd cell are placed next to each other in the cell width direction in the cell architecture, and
wherein the one-fin connector of the 1 st cell and the connector of the 2 nd cell are merged.
5. The cell architecture of claim 4 , wherein the connector of the 2 nd cell is formed around one fin which is the only fin of the 2 nd cell.
6. The cell architecture of claim 4 , further comprising a 3 rd cell which comprises an at least one-fin connector formed around at least one fin of the 3 rd cell for internal signal routing without being connected to a power rail of the 3 rd cell, and
wherein the 3 rd cell is placed next to the 2 nd cell such that the at least one fin of the 3 rd cell is placed next to the at least one fin of the 2 nd cell in the cell width direction in the cell architecture.
7. The cell architecture of claim 6 , wherein the at least one fin of the 3 rd cell and the only fin of the 2 nd cell are not merged.
8. The cell architecture of claim 6 , wherein the 3 rd cell further comprises another at least one-fin connector formed around another at least one fin of the 3 rd cell to connect at least one VFET included in the 3 rd cell to the power rail of the 3 rd cell, and
wherein the at least one fin of the 3 rd cell is placed between the other at least one fin of the 3 rd cell and the at least one fin of the 2 nd cell in the cell width direction in the cell architecture.
9. The cell architecture of claim 4 , wherein the connector of the 2 nd cell comprises an at least one-fin connector which is formed around at least one fin of the 2 nd cell, and connects at least one VFET of the 2 nd cell to the power rail of the 2 nd cell.
10. The cell architecture of claim 9 , wherein the one-fin connector of the 1 st cell comprises a one-fin bottom source/drain (S/D) region of the VFET of the 1 st cell, and the at least one-fin connector of the 2 nd cell comprises an at least one-fin bottom S/D region of the at least one VFET of the 2 nd cell.
11. The cell architecture of claim 9 , wherein the one-fin connector of the 1 st cell comprises a one-fin top source/drain (S/D) contact structure formed on a top S/D region of the VFET of the 1 st cell, and the at least one-fin connector of the 2 nd cell comprises an at least one-fin top S/D contact structure formed on at least one top S/D region of the at least one VFET of the 2 nd cell.
12. The cell architecture of claim 9 , wherein the 1 st cell and the 2 nd constitute a 1 st logic circuit and a 2 nd logic circuit, respectively, which are configured to perform a same logic function or operation.
13. The cell architecture of claim 9 , wherein the 1 st cell and the 2 nd constitute a 1 st logic circuit and a 2 nd logic circuit, respectively, which are configured to perform different logic functions or operations.
14. The cell architecture of claim 9 , wherein the at least one VFET of the 2 nd cell is an at least one dummy VFET configured to not receive a gate input signal.