Hybrid electric variable speed drive
A specialized variable speed drive of the present invention is capable of controlling a motor and increasing the efficiency of both an ACIM or DCBL motor by biasing operation in favor of a class AB mode. The variable speed drive may be configured with two gate drivers where one gate driver is a class D gate driver and the second gate driver is either a class AB gate driver or a class C gate driver. The system also operates to reduce electro-magnetic interference in the operation of motors while increasing the reliability of the overall VSD system.
1. A variable speed drive for controlling a motor said drive comprising:
an embedded system block comprising:
an input module capable of receiving inputs from a user of said variable speed drive;
a processor for processing said inputs from said user;
memory; and
an output module;
a hardware block comprising:
a switch controlled by said processor;
a first gate driver wherein said first gate driver is a class D gate driver;
a second gate driver wherein said second gate driver is a class AB gate driver or a class C gate driver;
a bridge for converting a high power DC supply to AC power to operate said motor; and
software residing on said memory wherein said processor will execute said software to control said motor wherein said processor will generate at least one of:
a first signal wherein when said first signal is generated, said processor will operate said switch so that said first signal can be sent to said first gate driver; or
a second signal wherein when said second signal is generated, said processor will operate said switch so that said second signal can be sent to said second gate driver.
2. The variable speed drive of claim 1 further comprising:
a sensor wherein said sensor can measure data comprising at least one of:
current of said motor;
rotor position of said motor;
revolutions per minute of said motor;
angular speed of said motor; or
torque of said motor.
3. The variable speed drive of claim 2 wherein said measured angular speed and said measured torque of said motor are transmitted to said processor in real time wherein said processor will analyze said measured angular speed and torque wherein said analysis will comprise:
multiplying said measured torque by said measured angular speed to obtain a mechanical power value;
comparing said mechanical power value by a predetermined power level;
generating one or more of:
a first output to be delivered to said first gate driver; and
a second output to be delivered to said second gate driver;
delivering said first output to said first gate driver when said mechanical power value is greater than said predetermined power level and delivering said second output to said second gate driver when mechanical power value is less than said predetermined power level.
4. The variable speed drive of claim 3 wherein said first output is a Pulse Width Modulated (PWM) signal.
5. The variable speed drive of claim 3 wherein said second output is a 3-phase sinusoidal signal.
6. The variable speed drive of claim 3 wherein said second output is a trapezoidal signal.
7. The variable speed drive of claim 1 wherein said software residing on said memory is a V/Hz algorithm.
8. The variable speed drive of claim 2 wherein said software residing on said memory is a Field Oriented Control algorithm.
9. The variable speed drive or claim 8 wherein said processor will use said measured data in executing said Field Oriented Control algorithm.
10. The variable speed drive of claim 1 wherein said input module is a field programmable gate array.
11. The variable speed drive of claim 1 wherein said input module is comprised of discrete electronic components.
12. The variable speed drive of claim 1 wherein said output module comprises:
a sinusoidal oscillator.
13. The variable speed drive of claim 12 wherein said sinusoidal oscillator propagates the differential equation dx/dt=A·ω·x/2 wherein said equation is transformed to a difference equation via the Bilinear Transformation method of:
X ( n+ 1)=inv(2· I− 0·5· A·ω·T )·(2· I+ 0·5· A·ω·T )· X ( n ).
14. The variable speed drive of claim 1 wherein said output module generates signals to be transmitted to at least one of:
said first gate driver; or
said second gate driver.
15. The variable speed drive of claim 14 wherein said generated signals comprise at least one of:
a 3-phase Pulse Width Modulation (PWM) signal;
a 3-phase sinusoidal signal; or
a trapezoidal signal.
16. The variable speed drive of claim 1 wherein said processor will execute said software to generate at least one of:
a first signal wherein when said first signal is generated, said processor will operate said switch so that said first signal can be sent to said first gate driver; or
a second signal wherein when said second signal is generated, said processor will operate said switch so that said second signal can be sent to said second gate driver.
17. The variable speed drive of claim 16 wherein said hardware block further comprises a digital to analog converter wherein said second signal is a digital sinusoidal signal wherein said digital to analog converter will convert said digital sinusoidal signal to an analog signal to be sent to said second gate driver.
18. The variable speed drive of claim 1 wherein said bridge is a PA93 high voltage, low quiescent current MOSFET operational amplifier.
19. The variable speed drive of claim 1 wherein said second gate driver is integrated with said bridge in three PA93 high voltage, low quiescent current MOSFET operational amplifiers.
20. A system for controlling a motor comprising:
a power supply;
a variable speed drive wherein said variable speed drive comprises:
an embedded system block comprising:
an input module capable of receiving inputs from a user of said variable speed drive;
a processor for processing said inputs from said user;
memory; and
an output module;
a hardware block comprising:
a switch controlled by said processor;
a first gate driver;
a second gate driver; and
a bridge for converting a high power DC supply to AC power to operate said motor; and
software residing on said memory to be executed by said processor for controlling said motor.
21. The system of claim 20 wherein said power supply outputs a low voltage to power low voltage components and a high voltage for powering said motor.
22. The system of claim 21 wherein said first gate driver is a class D gate driver.
23. The system of claim 22 wherein said second gate driver is a class AB gate driver.
24. The system of claim 22 wherein said second gate driver is a class C gate driver.