Integrated circuit structure and method with hybrid orientation for FinFET
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
1. A semiconductor structure comprising:
a semiconductor substrate having a first region and a second region;
a first fin of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin has a <100> crystalline direction along the first direction;
a second fin of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin has a <110> crystalline direction along the first direction;
a dielectric feature configured to isolate the first fin from the semiconductor substrate, wherein the dielectric feature is a silicon oxide feature; and
a silicon layer underlying the second fin, wherein the silicon layer includes a top surface being coplanar with a top surface of the dielectric feature.
2. The semiconductor structure of claim 1 , further comprising:
an n-type field-effect transistor (nFET) formed on the first fin within the first region; and
a p-type field-effect transistor (pFET) formed on the second fin within the second region.
3. The semiconductor structure of claim 2 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.
4. The semiconductor structure of claim 1 , wherein the first fin continuously extends to the semiconductor substrate and the second fin includes multiple channels vertically stacked within the second regions.
5. The semiconductor structure of claim 4 , further comprising a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature.
6. The semiconductor structure of claim 5 , wherein the STI feature has a top surface being coplanar with a top surface of the dielectric feature and the STI feature has a bottom surface being below a bottom surface of the dielectric feature.
7. The semiconductor structure of claim 1 , wherein the silicon layer includes a bottom surface being coplanar with a bottom surface of the dielectric feature.
8. The semiconductor structure of claim 1 , wherein each of the first fin and the second fin is in a crystalline structure with a top surface on a (100) crystal plane.
9. The semiconductor structure of claim 8 , wherein the semiconductor substrate is a silicon substrate having a top surface on the (100) crystal plane.
10. The semiconductor structure of claim 9 , wherein the semiconductor substrate has a crystalline orientation <110> along the first direction.
11. A semiconductor structure comprising:
a semiconductor substrate having a first region and a second region;
a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, and being isolated from the semiconductor substrate by a dielectric feature, wherein the first fin active region has a <100> crystalline direction along the first direction;
a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction;
an n-type fin field-effect transistor (NFinFET) formed on the first fin active region; and
a p-type fin field-effect transistor (PFinFET) formed on the second fin active region; and
a silicon layer underlying the second fin active region, wherein the silicon layer includes a top surface being coplanar with a top surface of the dielectric feature.
12. The semiconductor structure of claim 11 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.
13. The semiconductor structure of claim 12 , wherein
each of the first fin active region and the second fin active region is in a crystalline structure with a top surface on a (100) crystal plane;
the semiconductor substrate is a silicon substrate having a top surface on the (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.
14. The semiconductor structure of claim 11 , wherein the silicon layer includes a bottom surface being coplanar with a bottom surface of the dielectric feature.
15. The semiconductor structure of claim 14 , further comprising a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature.
16. The semiconductor structure of claim 15 , wherein the STI feature has a top surface being coplanar with the top surface of the dielectric feature and the STI feature has a bottom surface being below a bottom surface of the dielectric feature.
17. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region;
a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, and being isolated from the semiconductor substrate by a dielectric feature, wherein the first fin active region has a <100> crystalline direction along the first direction;
a second fin active region of a second semiconductor material disposed on the semiconductor substrate within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction, the second semiconductor material being different from the first semiconductor material in composition;
a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature, wherein the STI feature has a top surface being coplanar with the top surface of the dielectric feature and the STI feature has a bottom surface being below a bottom surface of the dielectric feature; and
a silicon layer underlying the second fin active region, wherein the silicon layer includes a top surface being coplanar with a top surface of the dielectric feature, wherein
each of the first fin active region and the second fin active region is in a crystalline structure with a top surface on a (100) crystal plane;
the semiconductor substrate is a silicon substrate having a top surface on a (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.
18. The semiconductor structure of claim 17 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.
19. The semiconductor structure of claim 17 , wherein the dielectric feature spans between opposite edges of the first fin active region.
20. The semiconductor structure of claim 19 , wherein the silicon layer spans between opposite edges of the second fin active region.