IP Library › Granted Patent US 11,437,544
Granted Patent B2
US 11,437,544 · App. 16/742,909 · Granted Sep 6, 2022

Pixel for micro display and method of manufacturing the same

Inventors: James Chinmo Kim (San Jose, CA); Sungsoo Yi (Sunnyvale, CA)
H01L33/08H01L27/15H01L33/0075H01L33/06H01L33/145H01L33/24H01L33/325
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Quick Facts
Patent No.
US 11,437,544
App. No.
16/742,909
Granted
Sep 6, 2022
Kind
B2
Abstract

Disclosed are a unit pixel of a microdisplay and a method of manufacturing the same. In the unit pixel, each of the sub-pixels forming blue, green, and red light is vertically stacked on the growth substrate. As a result, the area of a unit pixel may be reduced, and transfer processes may be facilitated.

Claims (56)

1. A unit pixel of a microdisplay comprising:

a first sub-pixel formed on a growth substrate and configured to emit light of a first wavelength;

a common anode layer formed on the first sub-pixel and having n-type GaN;

a second sub-pixel formed on the common anode layer and emitting light of a second wavelength longer than the first wavelength;

a current blocking layer formed on the second sub-pixel and having a GaN-based compound semiconductor; and

a third sub-pixel formed on the current blocking layer and emitting light of a third wavelength longer than the second wavelength,

wherein the common anode layer comprises:

a first anode layer to which a positive voltage is applied and having n-type GaN;

a first tunnel junction layer disposed between the first anode layer and the first sub-pixel; and

a second tunnel junction layer disposed between the first anode layer and the second sub-pixel,

wherein the first tunnel junction layer comprises:

a first highly n-doped layer formed on the first anode layer; and

a first highly p-doped layer formed between the first highly n-doped layer and the first sub-pixel.

2. The unit pixel of claim 1 , wherein the second tunnel junction layer comprises:

a second highly n-doped layer formed on the first anode layer; and

a second highly p-doped layer formed between the second highly n-doped layer and the second sub-pixel.

3. The unit pixel of claim 1 , wherein the current blocking layer is p-type GaN or GaN doped with a transition metal.

4. The unit pixel of claim 3 , wherein the current blocking layer has GaN doped with Fe.

5. The unit pixel of claim 1 , wherein the third sub-pixel comprises:

a third n-type semiconductor layer formed on the current blocking layer;

a third active layer formed on the third n-type semiconductor layer; and

a third p-type semiconductor layer formed on the third active layer.

6. The unit pixel of claim 5 , wherein the third sub-pixel further comprises a growth limiting layer formed on the current blocking layer,

wherein the third n-type semiconductor layer is formed in lateral spaces between islands or empty spaces of a mesh formed by the growth limiting layer and grown based on the current blocking layer.

7. The unit pixel of claim 6 , wherein the third n-type semiconductor layer has a textured surface with sharp shapes and inclined side surfaces.

8. The unit pixel of claim 7 , wherein the third active layer is formed along a surface profile of the third n-type semiconductor layer.

9. The unit pixel of claim 6 , wherein the growth limiting layer has SiNx and is formed as an island type or a mesh type.

10. The unit pixel of claim 5 , wherein the current blocking layer comprises:

a growth limiting layer formed on the second sub-pixel; and

a blocking semiconductor layer formed in lateral spaces between islands or empty spaces of a mesh formed by the growth limiting layer.

11. The unit pixel of claim 10 , wherein the growth limiting layer has SiNx and is formed as an island type or a mesh type.

12. The unit pixel of claim 10 , wherein the blocking semiconductor layer is p-type GaN or GaN doped with a transition metal.

13. The unit pixel of claim 10 , wherein the blocking semiconductor layer is doped with Mg or Fe.

14. The unit pixel of claim 10 , wherein the blocking semiconductor layer has sharp shapes and inclined side surfaces.

15. The unit pixel of claim 14 , wherein the third n-type semiconductor layer is formed along a surface profile of the blocking semiconductor layer.

16. The unit pixel of claim 5 , wherein the common anode layer and the third p-type semiconductor layer of the third sub-pixel are commonly connected to a common electrode.

17. A method of manufacturing a unit pixel of microdisplay comprising:

forming a first sub-pixel on a growth substrate to emit light of a first wavelength by using a GaN-based compound semiconductor;

forming a common anode layer having GaN on the first sub-pixel;

forming a second sub-pixel having GaN on the common anode layer and to emit light of a second wavelength longer than the first wavelength;

forming a current blocking layer having GaN on the second sub-pixel, and for blocking leakage current from or toward the second sub-pixel; and

forming a third sub-pixel having GaN on the current blocking layer, and to emit light of a third wavelength longer than the second wavelength,

wherein forming the third sub-pixel comprises:

forming a growth limiting layer having an island type or a mesh type on the current blocking layer;

forming a third n-type semiconductor layer in lateral spaces between islands or empty spaces of a mesh formed by the growth limiting layer based on an exposed current blocking layer;

forming a third active layer along a surface profile of the third n-type semiconductor layer; and

forming a third p-type semiconductor layer on the third active layer.

18. The method of claim 17 , wherein the third n-type semiconductor layer has sharp shapes and inclined side surfaces.

19. The method of claim 17 , wherein the current blocking layer has SiNx.

20. The method of claim 17 , wherein forming the current blocking layer comprises:

forming a growth limiting layer having SiNx, and having the island type or the mesh type on the second sub-pixel; and

forming a current blocking semiconductor layer grown according to a crystal structure of the second sub-pixel in lateral spaces between islands or empty spaces of a mesh formed by the growth limiting layer.

21. The method of claim 20 , wherein the blocking semiconductor layer has GaN doped with Mg or Fe.

22. The method of claim 17 , further comprising:

performing a pixel isolation process by etching to expose a portion of a surface of the growth substrate after forming the third sub-pixel; and

performing a heat treatment to discharge hydrogen atoms contained in p-type semiconductor layers through side surfaces exposed by the pixel isolation process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2020
From: KIM, JAMES CHINMO; YI, SUNGSOO
To: SUNDIODE KOREA
Reel/Frame 051514/0577 →
Priority Claims (1)
KR 10-2019-0127506 · Oct 15, 2019 · national
Continuity (1)
Related Publication 20210111306A1 · Apr 15, 2021
Cited By (1)
US 12,262,569