Three-dimensional memory devices having through array contacts and methods for forming the same
Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.
1. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising interleaved a plurality of conductive layers and dielectric layers, each of the plurality of conductive layers having a respective shallow recess;
a channel structure extending vertically through the memory stack; and
a through array contact (TAC) extending vertically through the memory stack,
wherein the TAC comprises a conductor layer and a spacer in the plurality of shallow recesses abutting a sidewall of the TAC.
2. The 3D memory device of claim 1 , wherein the spacer is further over the sidewall of the TAC.
3. The 3D memory device of claim 1 , wherein the TAC is in an inner region of the memory stack.
4. The 3D memory device of claim 1 , further comprising a dummy channel structure filled with a dielectric layer and extending vertically through the memory stack.
5. The 3D memory device of claim 4 , wherein the dielectric layer in the dummy channel structure and the spacer in the TAC comprise silicon oxide.
6. The 3D memory device of claim 1 , further comprising:
a peripheral device on the substrate; and
a peripheral contact outside of the memory stack and in contact with the peripheral device.
7. The 3D memory device of claim 1 , further comprising a slit structure extending vertically through the memory stack.
8. The 3D memory device of claim 1 , wherein the memory stack comprises:
a lower memory deck on the substrate; and
an upper memory deck above the lower memory deck.
9. The 3D memory device of claim 8 , wherein the channel structure comprises:
a lower channel structure extending vertically through the lower memory deck;
an upper channel structure extending vertically through the upper memory deck; and
an inter-deck plug disposed vertically between and in contact with the lower channel structure and the upper channel structure.
10. The 3D memory device of claim 1 , further comprising:
a staircase structure at one side of the memory stack; and
a plurality of word line contacts each in contact with a respective one of the plurality of conductive layers in the staircase structure.
11. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising interleaved a plurality of conductive layers and dielectric layers, none of the plurality of conductive layers having a shallow recess;
a channel structure extending vertically through the memory stack; and
a through array contact (TAC) extending vertically through the memory stack,
wherein the TAC comprises a conductor layer and a spacer over a sidewall of the TAC.
12. The 3D memory device of claim 11 , further comprising a dummy channel structure filled with a dielectric layer and extending vertically through the memory stack.
13. The 3D memory device of claim 11 , further comprising:
a peripheral device on the substrate; and
a peripheral contact outside of the memory stack and in contact with the peripheral device.
14. The 3D memory device of claim 1 , wherein the TAC has a circular shape in a plan view.
15. The 3D memory device of claim 11 , wherein the TAC has a circular shape in a plan view.
16. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising interleaved a plurality of conductive layers and dielectric layers;
a channel structure extending vertically through the memory stack;
a source contact extending vertically through the memory stack; and
a through array contact (TAC) extending vertically through the memory stack,
wherein the TAC comprises a conductor layer and a spacer in a plurality of shallow recesses abutting a sidewall of the TAC.
17. The 3D memory device of claim 16 , wherein the TAC has a circular shape in a plan view.
18. The 3D memory device of claim 16 , further comprising a dummy channel structure filled with a dielectric layer and extending vertically through the memory stack.
19. The 3D memory device of claim 18 , wherein the dielectric layer in the dummy channel structure and the spacer in the TAC comprise silicon oxide.
20. The 3D memory device of claim 16 , further comprising:
a peripheral device on the substrate; and
a peripheral contact outside of the memory stack and in contact with the peripheral device.