System on integrated chips and methods of forming same
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.
1. A package comprising:
a first semiconductor die;
a first isolation material around the first semiconductor die;
a second semiconductor die over the first semiconductor die, the first semiconductor die and the second semiconductor die share a first insulator-to-insulator interface and a first metal-to-metal interface, the second semiconductor die and the first isolation material share a second insulator-to-insulator interface;
a second isolation material around the second semiconductor die; and
redistribution layers over the second semiconductor die, the redistribution layers are electrically connected to the first semiconductor die and the second semiconductor die.
2. The package of claim 1 further comprising:
a third semiconductor die, the third semiconductor die and the second semiconductor die share a third insulator-to-insulator interface and a second metal-to-metal interface.
3. The package of claim 2 , wherein the first isolation material is disposed around the third semiconductor die.
4. The package of claim 1 , wherein the redistribution layers are electrically connected to the first semiconductor die by a conductive via, the conductive via extends along a sidewall of the second semiconductor die, and the second semiconductor die is physically separated from the conductive via by the second isolation material.
5. The package of claim 4 , wherein the conductive via extends through an insulator layer of the first semiconductor die.
6. The package of claim 4 , wherein the conductive via extends to a contact pad at a top surface of the first semiconductor die.
7. The package of claim 1 further comprising a dummy die surrounded by the first isolation material.
8. The package of claim 7 , wherein the first isolation material separates a top surface of the dummy die from a bottom surface of the second semiconductor die.
9. The package of claim 7 , wherein the dummy die and the second semiconductor die share a fourth insulator-to-insulator interface.
10. The package of claim 1 , wherein the first semiconductor die and the second isolation material share a fifth insulator-to-insulator interface.
11. A package comprising:
a first semiconductor die;
a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;
a first isolation material surrounding the second semiconductor die;
a conductive via extending through the first isolation material and the first dielectric layer; and
a redistribution structure electrically connected to the first semiconductor die by the conductive via.
12. The package of claim 11 , wherein a first contact pad of the first semiconductor die is directly bonded to a second contact pad of the second semiconductor die.
13. The package of claim 11 further comprising a third semiconductor die laterally separated from the first semiconductor die, wherein a third dielectric layer of the third semiconductor die is directly bonded to the second dielectric layer, and wherein a fourth contact pad of the third semiconductor die is directly bonded to a fifth contact pad of the second semiconductor die.
14. The package of claim 13 further comprising a second conductive via electrically connecting the redistribution structure to the third semiconductor die, the second conductive via extends through the first isolation material.
15. The package of claim 11 further comprising a second isolation material around the first semiconductor die.
16. A semiconductor package comprising:
a first semiconductor die;
a second semiconductor die, wherein a first dielectric layer of the first semiconductor die touches a second dielectric layer of the second semiconductor die, and wherein a first contact pad the first semiconductor die touches a second contact pad of the second semiconductor die;
an isolation material disposed around the first semiconductor die; and
a first conductive via electrically connecting a redistribution structure to the second semiconductor die, wherein the first conductive via extends along a sidewall of the first semiconductor die, and the isolation material is between a sidewall of the first conductive via and the sidewall of the first semiconductor die.
17. The semiconductor package of claim 16 first comprising:
a third semiconductor die, wherein a third dielectric layer of the third semiconductor die touches the first dielectric layer of the first semiconductor die, and wherein a third contact pad of the third semiconductor die touches a fourth contact pad of the first semiconductor die; and
a second isolation material around the second semiconductor die and the third semiconductor die.
18. The semiconductor package of claim 17 further comprising a second conductive via electrically connecting the redistribution structure to the third semiconductor die, the second conductive via and the first conductive via are on opposing sides of the first semiconductor die.
19. The semiconductor package of claim 17 further comprising a dummy die in the second isolation material.
20. The semiconductor package of claim 19 , wherein a fourth dielectric layer of the dummy die touches the first dielectric layer of the first semiconductor die.