Package structure and fabrication methods
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
1. A package assembly, comprising:
a frame having a first surface opposite a second surface, the frame further comprising:
a frame material that comprises silicon;
at least one cavity with a semiconductor die disposed therein, the cavity extending through the frame from the first surface to the second surface; and
a via comprising a via surface that defines an opening extending through the frame from the first surface to the second surface;
an insulating layer disposed over the first surface, the second surface, the via surface, and surfaces of the at least one cavity, the insulating layer contacting each side of the semiconductor die;
an oxide layer formed on the first surface and the second surface of the frame, the via surface, and sidewalls of the at least one cavity, the oxide layer disposed between the frame and the insulating layer; and
an electrical interconnection disposed within the via, wherein the insulating layer is disposed between the via surface and the electrical interconnection.
2. The package assembly of claim 1 , wherein the frame comprises a solar substrate.
3. The package assembly of claim 1 , wherein the frame has a thickness between about 60 μm and about 160 μm.
4. The package assembly of claim 1 , wherein the at least one cavity has lateral dimensions between about 3 mm and about 50 mm.
5. The package assembly of claim 4 , wherein the lateral dimensions of the at least one cavity are greater than lateral dimensions of the semiconductor die by less than about 150 μm.
6. The package assembly of claim 1 , wherein the via has a diameter between about 20 μm and about 200 μm.
7. The package assembly of claim 1 , wherein the insulating layer comprises an epoxy resin.
8. The package assembly of claim 7 , wherein the epoxy resin comprises ceramic particles.
9. The package assembly of claim 8 , wherein the ceramic particles comprise silica particles.
10. The package assembly of claim 7 , wherein the insulating layer has a thickness between about 5 μm and about 50 μm between the electrical interconnection and the semiconductor die.
11. The package assembly of claim 1 , further comprising an adhesion layer or a seed layer disposed between the electrical interconnection and the insulating layer.
12. The package assembly of claim 11 , wherein the adhesion layer comprises molybdenum and the seed layer comprises copper.
13. A package assembly, comprising:
an embedded die assembly, comprising:
a frame that comprises silicon, the frame comprising one or more cavities and one or more vias formed through a thickness of the frame;
an oxide layer disposed over a first surface and a second surface of the frame, the oxide layer further disposed over sidewalls of the one or more cavities and the one or more vias;
one or more semiconductor dies disposed within the cavities of the frame, the one or more semiconductor dies having an integrated circuit formed thereon; and
an insulating layer formed on each outer surface of the oxide layer, the insulating layer comprising an epoxy resin material having ceramic particles disposed therein, the insulating layer disposed over the first surface and the second surface of the frame and extending through the one or more cavities and the one or more vias; and
one or more metal interconnections disposed within a portion of the embedded die assembly, the one or more metal connections extending through the one or more vias in the frame and circumferentially surrounded by the insulating layer.
14. The package assembly of claim 13 , wherein the frame comprises a monocrystalline solar substrate.
15. The package assembly of claim 14 , wherein the frame thickness is between about 60 μm and about 160 μm.
16. The package assembly of claim 13 , wherein
the insulating layer contacts each surface of the one or more semiconductor dies.
17. The package assembly of claim 13 , further comprising:
a molybdenum adhesion layer and a copper seed layer disposed between each of the one or more metal interconnections and the insulating layer.
18. A package assembly, comprising:
an embedded die assembly, comprising:
a frame comprising:
silicon;
a first surface opposing a second surface; one or more holes extending from the first surface to the second surface;
at least one cavity extending from the first surface to the second surface; and
an oxide layer formed on the first surface and the second surface, surface of the one or more holes, and sidewalls of the at least one cavity;
one or more semiconductor dies disposed within the at least one cavity;
a first insulating layer formed on the frame and extending from the first surface to the second surface, the first insulating layer comprising an epoxy resin material comprising ceramic particles, wherein the oxide layer is disposed between the first insulating layer and the first surface, the second surface, the surface of the one or more holes, and the sidewalls of the at least one cavity of the frame; and
one or more electrical interconnections disposed through at least one of the one or more holes of the frame or and the first insulating layer; and
a redistribution layer formed on the embedded die assembly, the redistribution layer comprising:
a second insulating layer formed on the first insulating layer; and
one or more electrical redistribution connections disposed through the second insulating layer.
19. The package assembly of claim 18 , wherein the second insulating layer is formed of the same material as the first insulating layer.