IP Library › Granted Patent US 11,303,911
Granted Patent B1
US 11,303,911 · App. 16/749,416 · Granted Apr 12, 2022

Systems and methods for storing video data in memory

Inventor: Michael Scott (Menlo Park, CA)
Assignee: Xilinx, Inc.
H04N19/184H04N19/129H04N19/182H04N19/423H04N19/647
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Quick Facts
Patent No.
US 11,303,911
App. No.
16/749,416
Granted
Apr 12, 2022
Kind
B1
Abstract

Methods and systems for storing pixels of a video/image frame are disclosed. According to one embodiment, a method for storing pixels of a video frame comprises allocating a region of a memory to a pixel block having pixels of the video frame selected in out-of-raster-scan-order. The allocated region corresponds to a plurality of contiguous locations in the memory, and wherein the allocated region includes a first portion for storing pixel values. Values of pixels are stored in the pixel block in the first portion.

Claims (36)

1. A method for storing pixels of a video frame, the method comprising:

allocating a region of a memory to a pixel block having pixels of the frame selected in out-of-raster-scan-order, wherein the allocated region corresponds to a plurality of contiguous locations in the memory, and wherein the allocated region includes a first portion for storing pixel values; and

storing values of pixels in the pixel block in the first portion,

wherein the first portion has a set of sections, a subset of the set of sections having a size corresponding to a data size of a single read or write operation of the memory or a page of the memory, wherein each section corresponds to pixels from four rows and eight columns of the pixel block, and the subset comprises four sections.

2. The method of claim 1 , wherein the allocated region includes a second portion for storing auxiliary data.

3. The method of claim 1 , wherein the pixel block has pixels selected from 64 contiguous rows of the frame and 64 contiguous columns of the frame.

4. The method of claim 1 , wherein storing the values of pixels comprises storing luma values of the pixels in a luma buffer in the first portion and storing chroma values of the pixels in a chroma buffer in the first portion.

5. The method of claim 4 , wherein a size of the luma buffer is two times a size of the chroma buffer.

6. The method of claim 1 , wherein storing the values of pixels comprises storing least significant bits of the values in a first subsection of a first section in the set of sections, and storing most significant bits of the values in a second subsection of the first section.

7. The method of claim 1 , wherein storing the values of pixels comprises storing all bits of the values in a first subsection of a first section in the set of sections.

8. The method of claim 1 , further comprising:

generating the pixel block from raw video;

performing one or more pre-encoding operations on the pixel block, the one or more pre-encoding operations including reading the values of pixels in the pixel block from the first portion; and storing auxiliary data generated by the one or more pre-encoding operations in a second portion; and

encoding the pixel block by reading the values of pixels in the pixel block from the first portion and reading the auxiliary data from the second portion.

9. The method of claim 1 , further comprising:

repeating the allocating and storing steps with respect to another pixel block having different pixels of the frame selected in the out-of-raster-scan-order, wherein the allocated regions are contiguous with respect to each other.

10. The method of claim 1 , wherein the memory is a DDR memory.

11. A storage module comprising:

a first region of memory allocated to a first pixel block having video frame pixels selected in out-of-raster-scan-order, wherein the first allocated region:

corresponds to a plurality of contiguous locations in the memory; and

includes a first portion for storing pixel values,

wherein the first portion has a set of sections, a subset of the set of sections having a size corresponding to a data size of a single read or write operation of the memory or a page of the memory, wherein each section corresponds to pixels from four rows and eight columns of the pixel block, and the subset comprises four sections.

12. The storage module of claim 11 , wherein the first allocated region includes a second portion for storing auxiliary data.

13. The storage module of claim 11 , wherein the first pixel block has pixels selected from 64 contiguous rows of the frame and 64 contiguous columns of the frame.

14. The storage module of claim 11 , wherein the first portion comprises:

a luma buffer for storing luma values of the pixels; and

a chroma buffer for storing chroma values of the pixels.

15. The storage module of claim 14 , wherein a size of the luma buffer is two times a size of the chroma buffer.

16. The storage module of claim 11 , wherein a first section in the set of sections comprises:

a first subsection for storing least significant bits of the pixel values; and

a second subsection for storing most significant bits of the pixel values.

17. The storage module of claim 11 , wherein a first section in the set of sections comprises:

a first subsection for storing all bits of the pixel values.

18. The storage module of claim 11 , further comprising:

a second region of the memory allocated to a second pixel block having video frame pixels that are: (i) different from the video frame pixels of the first pixel block, and (ii) selected in the out-of-raster-scan-order, wherein the allocated first region and the allocated second region are contiguous in the memory.

19. The storage module of claim 11 , wherein the memory is a DDR memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2021
From: SCOTT, MICHAEL
To: XILINX, INC.
Reel/Frame 058060/0284 →
Continuity (1)
Provisional Application 62795408 · Jan 22, 2019