IP Library › Granted Patent US 12,176,285
Granted Patent B2
US 12,176,285 · App. 16/750,225 · Granted Dec 24, 2024

Transformer guard trace

Inventor: Vijaylaxmi Gumaste Khanolkar (Pune, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L23/5227H01F17/0006H01F27/2804H01F27/288H01F41/041H01L23/495H01L24/32H01L24/48H05K3/4611H01L2224/32188H01L2224/48091H01L2224/73265H01L2924/1517
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Quick Facts
Patent No.
US 12,176,285
App. No.
16/750,225
Granted
Dec 24, 2024
Kind
B2
Abstract

An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.

Claims (85)

1. A packaged electronic device, comprising:

first conductive leads along a first side of a package structure;

second conductive leads along a second side of the package structure;

a first semiconductor die attached to a first die attach pad;

a second semiconductor die attached to a second die attach pad;

a magnetic assembly attached to a support structure in the package structure, the magnetic assembly including:

a multilevel lamination structure, including: a first patterned conductive feature having multiple turns in a first level to form a first winding, a second patterned conductive feature having multiple turns in a different level to form a second winding, and a conductive guard trace spaced apart from and between the first patterned conductive feature and the second side of the package structure;

a first core structure attached to a first side of the multilevel lamination structure; and

a second core structure attached to a second side of the multilevel lamination structure;

a first set of electrical connections that couple the first semiconductor die, the first patterned conductive feature, and at least one of the first conductive leads in a first circuit; and

a second set of electrical connections that couple the second semiconductor die, the second patterned conductive feature, the conductive guard trace, and at least one of the second conductive leads in a second circuit isolated from the first circuit.

2. The packaged electronic device of claim 1 , wherein the multilevel lamination structure includes a first conductive shield trace having multiple turns in a second level between the first patterned conductive feature and the second patterned conductive feature, the first set of electrical connections coupling the first conductive shield trace to the first circuit.

3. The packaged electronic device of claim 2 , wherein the conductive guard trace is in the second level.

4. The packaged electronic device of claim 2 , wherein the conductive guard trace is in at least one of the first level and the second level.

5. The packaged electronic device of claim 4 , wherein the multilevel lamination structure includes a second conductive shield trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature, the second conductive shield trace being coupled to the conductive guard trace in the second circuit.

6. The packaged electronic device of claim 4 , wherein:

the first and second sides of the package structure are spaced apart from one another along a first direction;

an outermost turn of the first patterned conductive feature has a first length along a second direction, the second direction being perpendicular to the first direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

7. The packaged electronic device of claim 2 , wherein:

the first and second sides of the package structure are spaced apart from one another along a first direction;

an outermost turn of the first patterned conductive feature has a first length along a second direction, the second direction being perpendicular to the first direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

8. The packaged electronic device of claim 1 , wherein:

the first and second sides of the package structure are spaced apart from one another along a first direction;

an outermost turn of the first patterned conductive feature has a first length along a second direction, the second direction being perpendicular to the first direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

9. A magnetic assembly, comprising:

a multilevel lamination structure, including:

a first side;

a second side spaced apart from the first side along a first direction;

a third side;

a fourth side spaced apart from the third side along a second direction, the second direction being perpendicular to the first direction;

a first patterned conductive feature having multiple turns in a first level to form a first winding;

a second patterned conductive feature having multiple turns in a different level to form a second winding; and

a conductive guard trace spaced apart from and between the first patterned conductive feature and the second side of the multilevel lamination structure;

a first core structure attached to the first side of the multilevel lamination structure; and

a second core structure attached to the second side of the multilevel lamination structure.

10. The magnetic assembly of claim 9 , wherein the multilevel lamination structure includes a first conductive shield trace having multiple turns in a second level between the first patterned conductive feature and the second patterned conductive feature.

11. The magnetic assembly of claim 10 , wherein the conductive guard trace is in the second level.

12. The magnetic assembly of claim 10 , wherein the conductive guard trace is in at least one of the first level and the second level.

13. The magnetic assembly of claim 12 , wherein the multilevel lamination structure includes a second conductive shield trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature.

14. The magnetic assembly of claim 12 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

15. The magnetic assembly of claim 10 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

16. The magnetic assembly of claim 9 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

17. A packaged electronic device, comprising:

first conductive leads along a first side of a package structure;

second conductive leads along a second side of the package structure;

a first semiconductor die attached to a first die attach pad;

a second semiconductor die attached to a second die attach pad;

a magnetic assembly attached to a support structure in the package structure, the magnetic assembly including:

a multilevel lamination structure, including: a first patterned conductive feature having multiple turns in a first level to form a first winding, a second patterned conductive feature having multiple turns in a different level to form a second winding, and a conductive guard trace spaced apart from and between the first patterned conductive feature and the second side of the package structure;

a first set of electrical connections that couple the first semiconductor die, the first patterned conductive feature, and at least one of the first conductive leads in a first circuit; and

a second set of electrical connections that couple the second semiconductor die, the second patterned conductive feature, the conductive guard trace, and at least one of the second conductive leads in a second circuit isolated from the first circuit.

18. The packaged electronic device of claim 17 , further including a core structure attached to a side of the multilevel lamination structure adjacent the first patterned conductive feature.

19. The packaged electronic device of claim 17 , further including a core structure attached to a side of the multilevel lamination structure adjacent the second patterned conductive feature.

20. A multilevel lamination structure, comprising:

a first side;

a second side spaced apart from the first side along a first direction;

a third side;

a fourth side spaced apart from the third side along a second direction, the second direction being perpendicular to the first direction;

a first patterned conductive feature having multiple turns in a first level to form a first winding;

a second patterned conductive feature having multiple turns in a different level to form a second winding; and

a conductive guard trace spaced apart from and between the first patterned conductive feature and the second side of the multilevel lamination structure.

21. The multilevel lamination structure of claim 20 , further including a first core structure attached to the third side of the multilevel lamination structure.

22. The multilevel lamination structure of claim 21 , further including a second core structure attached to the fourth side of the multilevel lamination structure.

23. The multilevel lamination structure of claim 20 , wherein the multilevel lamination structure includes a first conductive shield trace having multiple turns in a second level between the first patterned conductive feature and the second patterned conductive feature.

24. The multilevel lamination structure of claim 23 , wherein the conductive guard trace is in the second level.

25. The multilevel lamination structure of claim 24 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

26. The multilevel lamination structure of claim 23 , wherein the conductive guard trace is in at least one of the first level and the second level.

27. The multilevel lamination structure of claim 26 , wherein the multilevel lamination structure includes a second conductive shield trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature.

28. The multilevel lamination structure of claim 26 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

29. The multilevel lamination structure of claim 23 , wherein:

an outermost turn of the first patterned conductive feature has a first length along the second direction; and

the conductive guard trace has a second length along the second direction, the second length being greater than the first length.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2020
From: KHANOLKAR, VIJAYLAXMI GUMASTE
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 051960/0341 →
Priority Claims (1)
IN 201941004011 · Feb 1, 2019 · national
Continuity (2)
Continuation In Part 16236730 · Dec 31, 2018
Related Publication 20200211961A1 · Jul 2, 2020