Semiconductor device with sidewall oxidized dielectric and method for fabricating the same
The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.
1. A semiconductor device, comprising:
a substrate;
a tunneling insulating layer disposed over the substrate;
a floating gate disposed over the tunnel oxide layer;
a lateral oxidized intervention layer disposed over the floating gate, wherein the lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion;
a control gate disposed over the dielectric layer;
a plurality of doped regions disposed in the substrate and adjacent to sides of the tunneling insulating layer;
a plurality of lightly-doped regions disposed in the substrate and adjacent to sides of the lateral oxidized intervention layer;
a plurality of diffusion regions disposed in the substrate and between adjacent pairs of the plurality of lightly-doped regions;
a first well region disposed in the substrate, wherein the plurality of doped regions are disposed in the first well region; and
a second well region disposed in the substrate and separated from the first well region, wherein the control gate, the plurality of lightly-doped regions, and the plurality of diffusion regions are disposed in the second well region.
2. The semiconductor device of claim 1 , further comprising a plurality of memory unit spacers attached to the sidewall portion of the lateral oxidized intervention layer.
3. The semiconductor device of claim 2 , further comprising a memory unit capping layer disposed over the control gate.
4. The semiconductor device of claim 2 , wherein the lateral oxidized intervention layer has a thickness between 10 angstroms and about 350 angstroms.
5. The semiconductor device of claim 2 , wherein the tunneling insulating layer has a thickness different from a thickness of the lateral oxidized intervention layer, and the tunneling insulating layer is formed from a material different from that of the lateral oxidized intervention layer.
6. The semiconductor device of claim 2 , wherein the lateral oxidized intervention layer comprises a bottom lateral oxidized intervention layer disposed over the control gate, a middle lateral oxidized intervention layer disposed over the bottom lateral oxidized intervention layer, and a top lateral oxidized intervention layer disposed over the middle lateral oxidized intervention layer.