PAM-based coding schemes for parallel communication

1. An article of manufacture comprising an encoder for encoding data according to a coding scheme, the encoder comprising:

a first coding stage configured to convert N bits b 1 -b N of input data into P bits of intermediate data; and

a second coding stage configured to convert the P bits of intermediate data into M voltage signals w 1 -w M for transmission over M parallel wires to a decoder, wherein:

the coding scheme is an N-bit, M-wire PAM-Q code in which (i) each N-bit input value is encoded as a set of M voltage signals w 1 -w M , (ii) each voltage signal w i has one of Q voltage levels l 1 -l Q , where l 1 <l 2 < . . . <l Q , and (iii) the different sets of M voltage signals w 1 -w M for the different N-bit input values are permutations of a single set of M voltage signals; and

for each N-bit input, the M voltage signals are decodable by the decoder having a comparator stage and no more than one other decoding stage, wherein, for the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.

2. The article of claim 1 , wherein N=M=Q=4.

3. The article of claim 2 , wherein the 4-bit, 4-wire PAM4 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 2 l 3 l 4 )

(0 0 0 1)

(l 1 l 2 l 4 l 3 )

(0 0 1 0)

(l 2 l 3 l 4 l 1 )

(0 0 1 1)

(l 1 l 3 l 4 l 2 )

(0 1 0 0)

(l 1 l 3 l 2 l 4 )

(0 1 0 1)

(l 2 l 3 l 1 l 4 )

(0 1 1 0)

(l 1 l 4 l 2 l 3 ); (l 2 l 4 l 3 l 1 ); (l 3 l 4 l 1 l 2 )

(0 1 1 1)

(l 1 l 4 l 3 l 2 ); (l 2 l 4 l 1 l 3 ); (l 3 l 4 l 2 l 1 )

(1 0 0 0)

(l 4 l 1 l 2 l 3 ); (l 2 l 1 l 3 l 4 ); (l 3 l 1 l 4 l 2 )

(1 0 0 1)

(l 4 l 1 l 3 l 2 ); (l 3 l 1 l 2 l 4 ); (l 2 l 1 l 4 l 3 )

(1 0 1 0)

(l 3 l 2 l 4 l 1 )

(1 0 1 1)

(l 4 l 2 l 3 l 1 )

(1 1 0 0)

(l 4 l 2 l 1 l 3 )

(1 1 0 1)

(l 3 l 2 l 1 l 4 )

(1 1 1 0)

(l 4 l 3 l 1 l 2 )

(1 1 1 1 )

 (l 4 l 3 l 2 l 1 ).

4. The article of claim 1 , wherein N=4, M=5, and Q=3.

5. The article of claim 4 , wherein the 4-bit, 5-wire PAM3 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 5 w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 3 l 1 l 2 l 2 )

(0 0 0 1)

(l 1 l 2 l 1 l 2 l 3 )

(0 0 1 0)

(l 1 l 3 l 2 l 1 l 2 )

(0 0 1 1)

(l 1 l 2 l 2 l 1 l 3 )

(0 1 0 0)

(l 2 l 3 l 1 l 2 l 1 )

(0 1 0 1)

(l 1 l 2 l 2 l 3 l 1 )

(0 1 1 0)

(l 2 l 3 l 2 l 1 l 1 )

(0 1 1 1)

(l 1 l 2 l 3 l 2 l 1 )

(1 0 0 0)

(l 3 l 1 l 1 l 2 l 2 )

(1 0 0 1)

(l 2 l 1 l 1 l 2 l 3 )

(1 01 0)

(l 3 l 1 l 2 l 1 l 2 )

(1 0 1 1)

(l 2 l 1 l 2 l 1 l 3 )

(1 1 0 0)

(l 3 l 2 l 1 l 2 l 1 )

(1 1 0 1)

(l 2 l 1 l 2 l 3 l 1 )

(1 1 1 0)

(l 3 l 2 l 2 l 1 l 1 )

(1 1 1 1)

 (l 2 l 1 l 3 l 2 l 1 ).

6. The article of claim 1 , wherein N=4, M=5, and Q=4.

7. The article of claim 6 , wherein the 4-bit, 5-wire PAM4 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 5 w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 4 l 1 l 2 l 3 )

(0 0 0 1)

(l 1 l 2 l 1 l 3 l 4 )

(0 0 1 0)

(l 1 l 4 l 2 l 1 l 3 )

(0 0 1 1)

(l 1 l 2 l 3 l 1 l 4 )

(0 1 0 0)

(l 2 l 4 l 1 l 3 l 1 )

(0 1 0 1)

(l 1 l 2 l 3 l 4 l 1 )

(0 1 1 0)

(l 2 l 4 l 3 l 1 l 1 )

(0 1 1 1)

(l 1 l 2 l 4 l 3 l 1 )

(1 0 0 0)

(l 4 l 1 l 1 l 2 l 3 )

(1 0 0 1)

(l 2 l 1 l 1 l 3 l 4 )

(1 0 1 0)

(l 4 l 1 l 2 l 1 l 3 )

(1 0 1 1)

(l 2 l 1 l 3 l 1 l 4 )

(1 1 0 0)

(l 4 l 2 l 1 l 3 l 1 )

(1 1 0 1)

(l 2 l 1 l 3 l 4 l 1 )

(1 1 1 0)

(l 4 l 2 l 3 l 1 l 1 )

(1 1 1 1)

 (l 2 l 1 l 4 l 3 l 1 ).

8. The article of claim 1 , wherein each voltage level appears only one time in each code.

9. The article of claim 1 , wherein two different voltage levels appear twice in each code.

10. The article of claim 1 , wherein one of the voltage levels appears twice in each code.

11. An article of manufacture comprising a decoder for decoding signals generated using a coding scheme, the decoder comprising one or two decoding stages including a first decoding stage, wherein:

the first decoding stage is configured to receive M voltage signals w 1 -w M from M parallel wires;

the decoder is configured to recover N bits b 1 -b N of data from the M voltage signals w 1 -w M ;

the coding scheme is an N-bit, M-wire PAM-Q code in which (i) each N-bit input value is encoded as a set of M voltage signals w 1 -w M , (ii) each voltage signal w i has one of Q voltage levels l 1 -l Q , where l 1 <l 2 < . . . <l Q , and (iii) the different sets of M voltage signals w 1 -w M for the different N-bit input values are permutations of a single set of M voltage signals; and

the M voltage signals w 1 -w M are decodable by the decoder having a comparator stage and no more than one other decoding stage, wherein, for the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.

12. The article of claim 11 , wherein N=M=Q=4.

13. The article of claim 12 , wherein the 4-bit, 4-wire PAM4 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 2 l 3 l 4 )

(0 0 0 1)

(l 1 l 2 l 4 l 3 )

(0 0 1 0)

(l 2 l 3 l 4 l 1 )

(0 0 1 1)

(l 1 l 3 l 4 l 2 )

(0 1 0 0)

(l 1 l 3 l 2 l 4 )

(0 1 0 1)

(l 2 l 3 l 1 l 4 )

(0 1 1 0)

(l 1 l 4 l 2 l 3 ); (l 2 l 4 l 3 l 1 ); (l 3 l 4 l 1 l 2 )

(0 1 1 1)

(l 1 l 4 l 3 l 2 ); (l 2 l 4 l 1 l 3 ); (l 3 l 4 l 2 l 1 )

(1 0 0 0)

(l 4 l 1 l 2 l 3 ); (l 2 l 1 l 3 l 4 ); (l 3 l 1 l 4 l 2 )

(1 0 0 1)

(l 4 l 1 l 3 l 2 ); (l 3 l 1 l 2 l 4 ); (l 2 l 1 l 4 l 3 )

(1 0 1 0)

(l 3 l 2 l 4 l 1 )

(1 0 1 1)

(l 4 l 2 l 3 l 1 )

(1 1 0 0)

(l 4 l 2 l 1 l 3 )

(1 1 0 1)

(l 3 l 2 l 1 l 4 )

(1 1 1 0)

(l 4 l 3 l 1 l 2 )

(1 1 1 1)

 (l 4 l 3 l 2 l 1 ).

14. The article of claim 13 , wherein the decoder comprises a comparator stage followed by a computation stage.

15. The article of claim 14 , wherein the decoder decodes the 4 voltage signals w 1 -w 4 according to:

b 4 =1( w 4 >w 3 );

b 3 =1( w 3 >w 2 );

b 2 =1( w 3 >w 1 ); and

b 1 =1( w 2 >w 1 )+1( w 4 >w 2 )−1( w 4 >w 1 ).

16. The article of claim 13 , wherein the decoder comprises a comparator stage followed by a logic stage.

17. The article of claim 16 , wherein the decoder decodes the 4 voltage signals according to:

b 4 =1( w 4 >w 3 );

b 3 =1( w 3 >w 2 );

b 2 =1( w 3 >w 1 ); and

b 1 =1( w 2 >w 1 )XOR1( w 4 >w 2 )XOR1( w 4 >w 1 ).

18. The article of claim 11 , wherein N=4, M=5, and Q=3.

19. The article of claim 18 , wherein the 4-bit, 5-wire PAM3 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 5 w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 3 l 1 l 2 l 2 )

(0 0 0 1)

(l 1 l 2 l 1 l 2 l 3 )

(0 0 1 0)

(l 1 l 3 l 2 l 1 l 2 )

(0 0 1 1)

(l 1 l 2 l 2 l 1 l 3 )

(0 1 0 0)

(l 2 l 3 l 1 l 2 l 1 )

(0 1 0 1)

(l 1 l 2 l 2 l 3 l 1 )

(0 1 1 0)

(l 2 l 3 l 2 l 1 l 1 )

(0 1 1 1)

(l 1 l 2 l 3 l 2 l 1 )

(1 0 0 0)

(l 3 l 1 l 1 l 2 l 2 )

(1 0 0 1)

(l 2 l 1 l 1 l 2 l 3 )

(1 0 1 0)

(l 3 l 1 l 2 l 1 l 2 )

(1 0 1 1)

(l 2 l 1 l 2 l 1 l 3 )

(1 1 0 0)

(l 3 l 2 l 1 l 2 l 1 )

(1 1 0 1)

(l 2 l 1 l 2 l 3 l 1 )

(1 1 1 0)

(l 3 l 2 l 2 l 1 l 1 )

(1 1 1 1)

 (l 2 l 1 l 3 l 2 l 1 ).

20. The article of claim 19 , wherein the decoder comprises a computation stage followed by a comparator stage.

21. The article of claim 20 , wherein the decoder decodes the 5 voltage signals according to:

b 4 =1( w 5 >w 4 );

b 3 =1(( w 3 +w 2 )/2> w 1 );

b 2 =1( w 3 >w 2 ); and

b 1 =1(( w 1 +w 2 +w 3 )/3>( w 4 +w 5 )/2.

22. The article of claim 11 , wherein N=4, M=5, and Q=4.

23. The article of claim 22 , wherein the 4-bit, 5-wire PAM4 code is represented as:

(b 4 b 3 b 2 b 1 )

(w 5 w 4 w 3 w 2 w 1 )

(0 0 0 0)

(l 1 l 4 l 1 l 2 l 3 )

(0 0 0 1)

(l 1 l 2 l 1 l 3 l 4 )

(0 0 1 0)

(l 1 l 4 l 2 l 1 l 3 )

(0 0 1 1)

(l 1 l 2 l 3 l 1 l 4 )

(0 1 0 0)

(l 2 l 4 l 1 l 3 l 1 )

(0 1 0 1)

(l 1 l 2 l 3 l 4 l 1 )

(0 1 1 0)

(l 2 l 4 l 3 l 1 l 1 )

(0 1 1 1)

(l 1 l 2 l 4 l 3 l 1 )

(1 0 0 0)

(l 4 l 1 l 1 l 2 l 3 )

(1 0 0 1)

(l 2 l 1 l 1 l 3 l 4 )

(1 0 1 0)

(l 4 l 1 l 2 l 1 l 3 )

(1 0 1 1)

(l 2 l 1 l 3 l 1 l 4 )

(1 1 0 0)

(l 4 l 2 l 1 l 3 l 1 )

(1 1 0 1)

(l 2 l 1 l 3 l 4 l 1 )

(1 1 1 0)

(l 4 l 2 l 3 l 1 l 1 )

(1 1 1 1)

 (l 2 l 1 l 4 l 3 l 1 ).

24. The article of claim 23 , wherein the decoder comprises a computation stage followed by a comparator stage.

25. The article of claim 24 , wherein the decoder decodes the 5 voltage signals according to:

b 4 =1( w 5 >w 4 );

b 3 =1(( w 3 +w 2 )/2> w 1 );

b 2 =1( w 3 >w 2 ); and

b 1 =1(( w 1 +w 2 +w 3 )/3>( w 4 +w 5 )/2.

26. The article of claim 11 , wherein each voltage level appears only one time in each code.

27. The article of claim 11 , wherein two different voltage levels appear twice in each code.

28. The article of claim 11 , wherein one of the voltage levels appears twice in each code.

29. The article of claim 11 , wherein the decoder is configured to recover the N bits from the M voltage signals generated using the coding scheme using an instance of the following equation:

b

^

n

=

∑

c

⁢

γ

⁢

c

(

k

)

·

1

⁢

(

∑

m

=

1

M

⁢

α

m

(

n

,

c

)

·

w

m

>

∑

m

=

1

M

⁢

β

m

(

n

⁢

⁢

c

)

·

w

m

)

,

1

≤

n

≤

N

wherein:

{circumflex over (b)} n is the n th recovered bit;

w m is the relative amplitude of the voltage signal on the m th wire;

α m (n,c) , β m (n,c) , and γ c (k) are weighting values;

∑

m

=

1

M

⁢

α

m

(

n

,

c

)

·

w

m

⁢

⁢

and

⁢

⁢

∑

m

=

1

M

⁢

β

m

(

n

,

c

)

·

w

m

are inner sums;

(

∑

m

=

1

M

⁢

α

m

(

n

,

c

)

·

w

m

>

∑

m

=

1

M

⁢

β

m

(

n

,

c

)

·

w

m

)

is a comparison;

1

⁢

(

∑

m

=

1

M

⁢

α

m

(

n

,

c

)

·

w

m

>

∑

m

=

1

M

⁢

β

m

(

n

,

c

)

·

w

m

)

is 1 if the comparison relation is true, and is 0 otherwise; and

∑

c

⁢

γ

c

(

k

)

·

1

⁢

(

∑

m

=

1

M

⁢

α

m

(

n

,

c

)

·

w

m

>

∑

m

=

1

M

⁢

β

m

(

n

,

c

)

·

w

m

)

is an outer sum.

30. The article of claim 29 , wherein the decoder comprises an initial computation stage that performs the inner sums, followed by a comparison stage that performs the comparisons, followed by a second computation stage that performs the outer sums.