IP Library › Granted Patent US 12,067,478
Granted Patent B2
US 12,067,478 · App. 16/757,283 · Granted Aug 20, 2024

PCM-based neural network device

Inventors: Yun Heub Song (Seongnam, KR); Cheng Li (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
G06N3/049G06N3/063G06N3/065G06N3/084G06N5/046G11C11/54G11C13/0004
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Quick Facts
Patent No.
US 12,067,478
App. No.
16/757,283
Granted
Aug 20, 2024
Kind
B2
Abstract

A phase change material (PCM)-based neural network device according to an embodiment comprises: a plurality of neurons disposed for input layers and output layers, respectively; a plurality of PCMs connecting input lines of the input layers and output lines of the output layers; and at least one backward spike generator (BSG) shared by the plurality of neurons, and generating spike on the basis of an output pulse outputted from each of the neurons of the output layers.

Claims (30)

1. A phase change material (PCM)-based neural network device comprising:

a plurality of neurons disposed on each of an input layer and an output layer;

a plurality of PCMs connecting between input lines of the input layer and output lines of the output layer; and

at least one backward spike generator (BSG) shared by the plurality of neurons disposed on the output layer, and the at least one BSG is configured to generate a spike based on an output pulse output from each of the neurons of the output layer.

2. The PCM-based neural network device of claim 1 , wherein each of the plurality of neurons included in the input layer includes different components from the plurality of neurons included in the output layer.

3. The PCM-based neural network device of claim 2 , wherein each of the neurons of the input layer includes a PMOS and an NMOS other than a backward pulse driver, and

wherein each of the neurons of the output layer includes a PMOS and an NMOS other than a forward pulse driver.

4. The PCM-based neural network device of claim 1 , further comprising:

at least one control circuit configured to synchronize timing of a pulse output from each of the plurality of neurons and synchronize timing of the shared backward spike generator.

5. The PCM-based neural network device of claim 4 , wherein the at least one control circuit is provided for each of the input and output layers.

6. The PCM-based neural network device of claim 5 , wherein the at least one control circuit includes:

a level-1 control circuit configured to synchronize timing of a pulse output from each of the neurons of the input layer;

a level-2 control circuit configured to synchronize timing of an output pulse output from each of the neurons of the output layer; and

a global control circuit configured to control the level-1 control circuit and the level-2 control circuit.

7. A phase change material (PCM)-based neural network device comprising:

a plurality of neurons disposed on each of an input layer, a hidden layer, and an output layer;

a plurality of PCMs connecting between input lines of the input layer and connection lines of the hidden layer and between connection lines of the hidden layer and output lines of the output layer; and

at least one backward spike generator (BSG) shared by at least one of the plurality of neurons disposed on the hidden layer or the plurality of neurons disposed on the output layer, and the at least BSG is configured to generate a spike based on a corresponding one of a pulse output from of the neurons of the hidden layer or an output pulse output from each of the neurons of the output layer.

8. The PCM-based neural network device of claim 7 , wherein each of the plurality of neurons includes different components compared to the plurality of neurons included in another of the input, hidden, and output layers.

9. The PCM-based neural network device of claim 8 , wherein each of the neurons of the input layer includes a PMOS and an NMOS other than a backward pulse driver, and

wherein each of the neurons of the hidden layer includes a PMOS and an NMOS other than a Winner-Takes-All (WTA) driver, and

wherein each of the neurons of the output layer includes a PMOS and an NMOS other than a forward pulse driver.

10. The PCM-based neural network device of claim 7 , further comprising:

at least one control circuit configured to synchronize timing of a pulse output from each of the plurality of neurons and synchronize timing of the shared backward spike generator.

11. The PCM-based neural network device of claim 10 , wherein the at least one control circuit is provided for each of the input, hidden, and output layers.

12. The PCM-based neural network device of claim 11 , wherein the at least one control circuit includes:

a level-1 control circuit configured to synchronize timing of a pulse output from each of the neurons of the input layer;

a level-2 control circuit configured to synchronize timing of a pulse output from each of the neurons of the hidden layer;

a level-3 control circuit configured to synchronize timing of an output pulse output from each of the neurons of the output layer; and

a global control circuit configured to control the level-1 control circuit, the level-2 control circuit, and the level-3 control circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2023
From: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 065732/0374 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2020
From: SONG, YUN HEUB; LI, CHENG
To: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
Reel/Frame 052432/0319 →
Priority Claims (1)
KR 10-2017-0134748 · Oct 17, 2017 · national
Continuity (1)
Related Publication 20200302268A1 · Sep 24, 2020