IP Library › Granted Patent US 11,350,050
Granted Patent B2
US 11,350,050 · App. 16/761,464 · Granted May 31, 2022

Semiconductor integrated circuit and imaging device

Inventor: Naohiko Kimizuka (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N5/37452H01L27/14612H01L27/14643H01L29/739
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,350,050
App. No.
16/761,464
Granted
May 31, 2022
Kind
B2
Abstract

In a solid-state imaging element provided with a differential pair of transistors, noise of a signal from the differential pair is reduced. The semiconductor integrated circuit includes a pixel circuit and a pair of TFETs (Tunnel Field Effect Transistors). In the semiconductor integrated circuit, the pixel circuit photoelectrically converts incident light to generate a pixel signal. Further, in the semiconductor integrated circuit, the pair of TFETs amplifies the difference between the pixel signal generated by the pixel circuit and a predetermined reference signal that changes with time, and outputs the amplified difference as a differential amplification signal.

Claims (37)

1. A semiconductor integrated circuit, comprising:

a pixel circuit configured to photoelectrically convert incident light to a pixel signal;

a pair of TFETs (Tunnel Field Effect Transistors) that includes a first TFET and a second TFET, wherein the pair of TFETs is configured to:

amplify a difference between the pixel signal and a reference signal, wherein the reference signal changes with time; and

output the amplified difference as a differential amplification signal; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) configured to supply a constant current to the pair of TFETs, wherein

a source of the first TFET and a source of the second TFET are connected to a drain of the MOSFET, and

a first area of a gate of the MOSFET is substantially equal to each of a second area of a gate of the first TFET and a third area of a gate of the second TFET.

2. The semiconductor integrated circuit according to claim 1 , further comprising

a plurality of pixel circuits in a two-dimensional lattice shape, wherein

the plurality of pixel circuits includes the pixel circuit, and

a respective pair of TFETs is for each pixel circuit of the plurality of pixel circuits.

3. The semiconductor integrated circuit according to claim 2 , further comprising

a data storage unit configured to acquire and store data, that indicates time until the differential amplification signal changes to a value different from an initial value, as pixel data.

4. The semiconductor integrated circuit according to claim 3 , further comprising a plurality of data storage units, wherein

the plurality of data storage units includes the data storage unit, and

a respective data storage unit of the plurality of data storage units is for each pixel circuit of the plurality of pixel circuits.

5. The semiconductor integrated circuit according to claim 3 , wherein the data storage unit is for each column that includes a set of pixel circuits, of the plurality of pixel circuits, in a specific direction.

6. The semiconductor integrated circuit according to claim 1 , further comprising:

a substrate;

an N-well layer on the substrate;

a pair of N layers including an N-type semiconductor; and

a P layer including a P-type semiconductor, wherein

the P layer and the pair of N layers are on the N-well layer,

the P layer is between the pair of N layers on the N-well layer,

each source of the pair of TFETs is in the P layer, and

each drain of the pair of TFETs is in the pair of N layers.

7. An imaging device, comprising:

a pixel circuit configured to photoelectrically convert incident light to a pixel signal;

a pair of TFETs (Tunnel Field Effect Transistors) that includes a first TFET and a second TFET, wherein the pair of TFETs is configured to:

amplify a difference between the pixel signal and a reference signal, wherein the reference signal changes with time; and

output the amplified difference as a differential amplification signal;

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) configured to supply a constant current to the pair of TFETs, wherein

a source of the first TFET and a source of the second TFET are connected to a drain of the MOSFET, and

a first area of a gate of the MOSFET is substantially equal to each of a second area of a gate of the first TFET and a third area of a gate of the second TFET;

a data storage unit configured to acquire and store time information, that indicates time until the differential amplification signal changes to a value different from an initial value, as pixel data; and

a processing unit configured to perform a specific processing on the pixel data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2020
From: KIMIZUKA, NAOHIKO
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 054677/0800 →
Priority Claims (1)
JP JP2017-217865 · Nov 13, 2017 · national
Continuity (1)
Related Publication 20200396408A1 · Dec 17, 2020