IP Library Granted Patent US 11,217,162
Granted Patent B2
US 11,217,162 · App. 16/762,043 · Granted Jan 4, 2022

Pixel driving circuit, pixel circuit, display panel and display apparatus

Inventors: Long Han (Beijing, CN); Libin Liu (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
G09G3/3233G09G2300/0809G09G2310/0286G09G2330/021G11C19/28
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Quick Facts
Patent No.
US 11,217,162
App. No.
16/762,043
Granted
Jan 4, 2022
Kind
B2
Abstract

The present disclosure discloses a pixel driving circuit, a pixel circuit, a display panel and a display apparatus, wherein the pixel driving circuit is used for driving a light-emitting element to emit light, and includes: a plurality of switching transistors, wherein each of the switching transistors is an oxide thin film transistor.

Claims (52)

1. A pixel circuit, comprising:

a shift register comprising a plurality of transistors, wherein each of the transistors is a low temperature polysilicon thin film transistor; and

a pixel driving circuit for driving a light-emitting element to emit light,

wherein the pixel driving circuit includes a plurality of switching transistors, the transistors have a type opposite to that of the switching transistors, the pixel circuit further comprises:

an inverter coupled to the shift register and the pixel driving circuit respectively,

wherein the shift register is configured to provide a first driving signal, the inverter is configured to invert the first driving signal to generate a second driving signal, and the pixel driving circuit is configured to control the light-emitting element according to the second driving signal, and

wherein the inverter comprises:

a ninth transistor having a control electrode coupled to a signal output terminal, a first electrode coupled to a first power supply terminal, and a second electrode coupled to a first electrode of an eleventh transistor;

a tenth transistor having a control electrode coupled to the signal output terminal, a first electrode coupled to the first power supply terminal, and a second electrode coupled to an inversion output terminal;

the eleventh transistor having a control electrode coupled to a first clock signal terminal, and a second electrode coupled to a second power supply terminal;

a twelfth transistor having a control electrode coupled to the second electrode of the ninth transistor, a first electrode coupled to the inversion output terminal, and a second electrode coupled to the second power supply terminal; and

a fifth capacitor having one terminal coupled to the control electrode of the twelfth transistor and the other terminal coupled to a second clock signal terminal.

2. The pixel circuit according to claim 1 , wherein all the transistors are of the same type.

3. The pixel circuit according to claim 2 , wherein when the transistors have the same type as that of the switching transistors, the shift register is configured to provide a first driving signal, and the pixel driving circuit is configured to control the light-emitting element according to the first driving signal.

4. The pixel circuit according to claim 1 , wherein transistors in the inverter have the same type as that of the transistors in the shift register.

5. The pixel circuit according to claim 1 , wherein the plurality of transistors in the shift register comprise:

a first transistor having a control electrode coupled to a first clock signal terminal, a first electrode coupled to a signal input terminal, and a second electrode coupled to a third iiode

a second transistor having a control electrode coupled to the third node, a first electrode coupled to the first clock signal terminal, and a second electrode coupled to a fourth node;

a third transistor having a control electrode coupled to the first clock signal terminal, a first electrode coupled to a second power supply terminal, and a second electrode coupled to the fourth node;

a fourth transistor having a control electrode coupled to the fourth node, a first electrode coupled to a first power supply terminal, and a second electrode coupled to a signal output terminal;

a fifth transistor having a control electrode coupled to the third node, a first electrode coupled to the signal output terminal, and a second electrode coupled to a second clock signal terminal;

a sixth transistor having a control electrode coupled to the fourth node, a first electrode coupled to the first power supply terminal, and a second electrode coupled to a first electrode of a seventh transistor; and

the seventh transistor having a control electrode coupled to the second clock signal terminal, and a second electrode coupled to the third node.

6. The pixel circuit according to claim 5 , further comprising:

a third capacitor having one terminal coupled to the third node and the other terminal coupled to the signal output terminal; and

a fourth capacitor having one terminal coupled to the fourth node and the other terminal coupled to the first power supply terminal.

7. The pixel circuit according to claim 1 , wherein the plurality of transistors in the shift register comprise:

a first transistor having a control electrode coupled to a first clock signal terminal, a first electrode coupled to a signal input terminal, and a second electrode coupled to a third node;

a second transistor having a control electrode coupled to the third node, a first electrode coupled to a first clock signal terminal, and a second electrode coupled to a fourth node;

a third transistor having a control electrode coupled to the first clock signal terminal, a first electrode coupled to a second power supply terminal, and a second electrode coupled to the fourth node;

a fourth transistor having a control electrode coupled to the fourth node, a first electrode coupled to a first power supply terminal, and a second electrode coupled to a signal output terminal;

a fifth transistor having a control electrode coupled to a second electrode of an eighth transistor, a first electrode coupled to the signal output terminal, and a second electrode coupled to a second clock signal terminal;

a sixth transistor having a control electrode coupled to the fourth node, a first electrode coupled to the first power supply terminal, and a second electrode coupled to a first electrode of a seventh transistor;

the seventh transistor having a control electrode coupled to the second clock signal terminal, and a second electrode coupled to the third node; and

the eighth transistor having a control electrode coupled to the first power supply terminal and a first electrode coupled to the third node.

8. The pixel circuit according to claim 7 , further comprising:

a third capacitor having one terminal coupled to the second electrode of the eighth transistor and the other terminal coupled to the signal output terminal; and

a fourth capacitor having one terminal coupled to the fourth node and the other terminal coupled to the first power supply terminal.

9. A display panel, comprising: the pixel circuit according to claim 1 .

10. A display apparatus comprising the display panel according to claim 9 .

11. The pixel driving circuit according to claim 1 , comprising:

a plurality of switching transistors comprising:

a first switching transistor having a control electrode coupled to a scanning signal terminal, a first electrode coupled to a data signal terminal, and a second electrode coupled to a first node;

a second switching transistor having a control electrode coupled to a reset signal terminal, a first electrode coupled to a signal input terminal, and a second electrode coupled to a second node; and

a third switching transistor having a control electrode coupled to a light-emitting control terminal, a first electrode coupled to a high-level power supply terminal, and a second electrode coupled to a first electrode of a driving transistor,

the driving transistor having a control electrode coupled to the first node and a second electrode coupled to the second node;

a first capacitor having one terminal coupled to the first node and the other terminal coupled to the second node; and

a second capacitor having one terminal coupled to the high-level power supply terminal and the other terminal coupled to the second node,

wherein each of the switching transistors is an oxide thin film transistor,

wherein the driving transistor is a low temperature polysilicon thin film transistor.

12. The pixel driving circuit according to claim 11 ,

wherein all the switching transistors are N-type transistors or all the switching transistors are P-type transistors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2020
From: HAN, LONG; LIU, LIBIN
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 052590/0271 →
Priority Claims (1)
CN 201910107162.8 · Feb 2, 2019 · national
Continuity (1)
Related Publication 20200342808A1 · Oct 29, 2020