IP Library › Granted Patent US 11,448,869
Granted Patent B2
US 11,448,869 · App. 16/765,547 · Granted Sep 20, 2022

Wafer

Inventors: Toshimitsu Kawai (Hamamatsu, JP); Katsumi Shibayama (Hamamatsu, JP); Takashi Kasahara (Hamamatsu, JP); Masaki Hirose (Hamamatsu, JP); Hiroki Oyama (Hamamatsu, JP); Yumi Kuramoto (Hamamatsu, JP)
Assignee: HAMAMATSU PHOTONICS K.K.
G02B26/001
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Quick Facts
Patent No.
US 11,448,869
App. No.
16/765,547
Granted
Sep 20, 2022
Kind
B2
Abstract

A wafer includes a substrate layer, a first mirror layer having a plurality of two-dimensionally arranged first mirror portions, and a second mirror layer having a plurality of two-dimensionally arranged second mirror portions. A plurality of Fabry-Perot interference filter portions are formed in an effective area, in each of the plurality of Fabry-Perot interference filter portions a gap is formed between the first mirror portion and the second mirror portion. A plurality of dummy filter portions are formed in a dummy area disposed along an outer edge of the substrate layer and surrounding the effective area, in each of the plurality of dummy filter portions an intermediate layer is provided between the first mirror portion and the second mirror portion. At least the second mirror portion is surrounded by the first groove in each of the plurality of Fabry-Perot interference filter portions and the plurality of dummy filter portions.

Claims (19)

1. A wafer comprising:

a substrate layer having a first surface and a second surface opposite to the first surface;

a first mirror layer having a plurality of first mirror portions two-dimensionally arranged on the first surface; and

a second mirror layer having a plurality of second mirror portions two-dimensionally arranged on the first mirror layer,

wherein a plurality of Fabry-Perot interference filter portions are formed in an effective area, in each of the plurality of Fabry-Perot interference filter portions a gap is formed between the first mirror portion and the second mirror portion facing each other and a distance between the first mirror portion and the second mirror portion facing each other varies by an electrostatic force,

a plurality of dummy filter portions are formed in a dummy area disposed along an outer edge of the substrate layer and surrounding the effective area, in each of the plurality of dummy filter portions an intermediate layer is provided between the first mirror portion and the second mirror portion facing each other, and

at least the second mirror portion is surrounded by a first groove opening on a side opposite to the substrate layer in each of the plurality of Fabry-Perot interference filter portions and the plurality of dummy filter portions.

2. The wafer according to claim 1 , wherein the first groove is continuous through the effective area and the dummy area and reaches the outer edge of the substrate layer when viewed in a direction in which the first mirror portion and the second mirror portion face each other.

3. The wafer according to claim 1 , further comprising a stress adjustment layer provided on the second surface,

wherein a second groove opening on an opposite side of the substrate layer is formed in the stress adjustment layer, and,

the second groove is formed so as to correspond to the first groove.

4. The wafer according to claim 1 , wherein the plurality of Fabry-Perot interference filter portions and the plurality of dummy filter portions are disposed so as to be symmetric about each of a first straight line and a second straight line passing through a center of the substrate layer and orthogonal to each other when viewed in the direction in which the first mirror portion and the second mirror portion face each other.

5. The wafer according to claim 1 , wherein a modified region is formed inside the substrate layer so as to correspond to the first groove.

6. The wafer according to claim 5 , further comprising an expanding tape attached to a second surface side with respect to the substrate layer.

7. The wafer according to claim 1 , wherein a mirror-removed portion is formed in a portion of the dummy area, in the mirror-removed portion at least a portion of the second mirror portion is removed.

8. The wafer according to claim 7 , wherein at least the first mirror portion is surrounded by the first groove in the mirror-removed portion.

9. The wafer according to claim 8 ,

wherein the mirror-removed portion is provided in plurality along the outer edge of the substrate layer in the dummy area,

the first groove is continuous through the effective area and the dummy area and reaches the outer edge of the substrate layer when viewed in the direction in which the first mirror portion and the second mirror portion face each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2020
From: KAWAI, TOSHIMITSU; SHIBAYAMA, KATSUMI; KASAHARA, TAKASHI; HIROSE, MASAKI; OYAMA, HIROKI; KURAMOTO, YUMI
To: HAMAMATSU PHOTONICS K.K.
Reel/Frame 052712/0155 →
Priority Claims (1)
JP JP2017-226085 · Nov 24, 2017 · national
Continuity (1)
Related Publication 20200310105A1 · Oct 1, 2020