IP Library › Granted Patent US 11,616,149
Granted Patent B2
US 11,616,149 · App. 16/768,810 · Granted Mar 28, 2023

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Takuya Handa (Tochigi, JP); Yasuharu Hosaka (Tochigi, JP); Shota Sambonsuge (Chiba, JP); Yasumasa Yamane (Kanagawa, JP); Kenichi Okazaki (Tochigi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/24
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Quick Facts
Patent No.
US 11,616,149
App. No.
16/768,810
Granted
Mar 28, 2023
Kind
B2
Abstract

A semiconductor device with improved reliability is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, and an insulator over the third oxide. The second oxide contains In, an element M (M is Al, Ga, Y, or Sn), and Zn. The first oxide and the third oxide each include a region whose In concentration is lower than that in the second oxide.

Claims (86)

1. A semiconductor device comprising:

a first oxide;

a second oxide over the first oxide;

a first conductor and a second conductor provided on the second oxide to be separated from each other;

a third conductor over the first conductor;

a fourth conductor over the second conductor;

a third oxide over the second oxide, the third conductor, and the fourth conductor; and

a first insulator provided over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor;

a fifth conductor provided in the opening; and

a second insulator provided between the third oxide and the fifth conductor,

wherein the second oxide contains In, an element M, M being Al, Ga, Y, or Sn, and Zn,

wherein top surfaces of the third oxide, the second insulator, and the fifth conductor are substantially aligned,

wherein the third conductor is in contact with a top surface of the second oxide, a top surface of the first conductor, and a side surface of the first conductor,

wherein the fourth conductor is in contact with the top surface of the second oxide, a top surface of the second conductor, and a side surface of the second conductor,

wherein each of the third conductor and the fourth conductor comprises a region overlapping with the fifth conductor, and

wherein the first oxide and the third oxide each include a region whose In concentration is lower than that in the second oxide.

2. A semiconductor device comprising:

a first oxide;

a second oxide over the first oxide;

a first conductor and a second conductor provided on the second oxide to be separated from each other;

a third conductor over the first conductor;

a fourth conductor over the second conductor;

a third oxide over the second oxide, the third conductor, and the fourth conductor;

a first insulator provided over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor;

a fifth conductor provided in the opening; and

a second insulator provided between the third oxide and the fifth conductor,

wherein the third oxide is in contact with a side surface and a top surface of the third conductor and a side surface and a top surface of the fourth conductor,

wherein top surfaces of the third oxide, the second insulator, and the fifth conductor are substantially aligned,

wherein the second oxide contains In, an element M, M being Al, Ga, Y, or Sn, and Zn,

wherein the third conductor is in contact with a top surface of the second oxide, a top surface of the first conductor, and a side surface of the first conductor,

wherein the fourth conductor is in contact with the top surface of the second oxide, a top surface of the second conductor, and a side surface of the second conductor,

wherein each of the third conductor and the fourth conductor comprises a region overlapping with the fifth conductor,

wherein the first oxide and the third oxide each include a region whose In concentration is lower than that in the second oxide, and

wherein an In concentration in the second insulator is lower than or equal to 1.0×10 17 atoms/cm 3 .

3. The semiconductor device according to claim 1 ,

wherein the third oxide comprises a first layer and a second layer over the first layer,

wherein the first layer contains substantially the same composition as the second oxide, and

wherein the second layer comprises a region whose In concentration is lower than that in the second oxide.

4. The semiconductor device according to claim 1 ,

wherein the fifth conductor is provided to face a side surface of the second oxide, and

wherein the third oxide and the second insulator are provided between the fifth conductor and the side surface of the second oxide.

5. The semiconductor device according to claim 1 ,

wherein the first oxide contains In, Ga, and Zn,

wherein the second oxide contains In, Ga, and Zn, and

wherein the third oxide contains Ga and Zn.

6. The semiconductor device according to claim 2 ,

wherein the third oxide comprises a first layer and a second layer over the first layer,

wherein the first layer contains substantially the same composition as the second oxide, and

wherein the second layer comprises a region whose In concentration is lower than that in the second oxide.

7. A semiconductor device comprising:

a first oxide over a substrate;

a second oxide over the first oxide;

a first conductor and a second conductor provided over the second oxide;

a third oxide over the second oxide;

a fourth oxide over the third oxide;

a third conductor provided on the first conductor and the second oxide,

a fourth conductor provided on the second conductor and the second oxide,

a first insulator provided over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor;

a fifth conductor provided in the opening; and

a second insulator provided between the fourth oxide and the fifth conductor,

wherein the third oxide is in contact with a side surface and a top surface of the third conductor and a side surface and a top surface of the fourth conductor,

wherein top surfaces of the third oxide, the second insulator, and the fifth conductor are substantially aligned,

wherein the third conductor is in contact with a top surface of the second oxide, a top surface of the first conductor, and a first side surface of the first conductor,

wherein the fourth conductor is in contact with the top surface of the second oxide, a top surface of the second conductor, and a first side surface of the second conductor,

wherein each of the third conductor and the fourth conductor comprises a region overlapping with the fifth conductor,

wherein each of the first oxide, the second oxide, and the third oxide comprises In and Zn,

wherein the fourth oxide comprises Zn, and

wherein the first oxide and the third oxide each include a region whose In concentration is lower than In concentration in the second oxide.

8. The semiconductor device according to claim 7 ,

wherein an In concentration in the second insulator is lower than or equal to 1.0×10 17 atoms/cm 3 .

9. The semiconductor device according to claim 7 ,

wherein each of the first oxide, the second oxide, the third oxide, and the fourth oxide further comprises an element M,

wherein the element M is Al, Ga, Y, or Sn.

10. The semiconductor device according to claim 7 ,

wherein each of the first oxide, the second oxide, the third oxide, and the fourth oxide further comprises Ga.

11. The semiconductor device according to claim 7 ,

wherein the third oxide is In—Ga—Zn oxide, and

wherein the fourth oxide is gallium oxide or a Ga—Zn oxide.

12. The semiconductor device according to claim 7 ,

wherein an indium concentration of the third oxide is higher than an indium concentration of the fourth oxide.

13. The semiconductor device according to claim 1 ,

wherein a distance in a channel length direction of a region where the third conductor overlaps with the fifth conductor is greater than or equal to 0 nm and less than or equal to 30 nm.

14. The semiconductor device according to claim 2 ,

wherein a distance in a channel length direction of a region where the third conductor overlaps with the fifth conductor is greater than or equal to 0 nm and less than or equal to 30 nm.

15. The semiconductor device according to claim 7 ,

wherein a distance in a channel length direction of a region where the third conductor overlaps with the fifth conductor is greater than or equal to 0 nm and less than or equal to 30 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: YAMAZAKI, SHUNPEI; HANDA, TAKUYA; HOSAKA, YASUHARU; SAMBONSUGE, SHOTA; YAMANE, YASUMASA; OKAZAKI, KENICHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 053681/0366 →
Priority Claims (1)
JP JP2017-235885 · Dec 8, 2017 · national
Continuity (1)
Related Publication 20210175361A1 · Jun 10, 2021
Cited By (1)
US 12,464,777