DRAM with selective epitaxial cell transistor
A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.
1. A dynamic random access memory device, comprising:
a semiconductor substrate having a doped diffusion region formed therein;
a vertical transistor structure formed on a surface of the doped diffusion region of the semiconductor substrate, the transistor structure including a semiconductor pillar and a gate dielectric layer formed at a side of the semiconductor pillar;
a wordline including an electrically conductive gate layer contacting the gate dielectric layer;
a bit line, separated from the doped diffusion region and electrically connected with the doped diffusion region of the semiconductor substrate through a bit line contact structure, wherein the bit line contact is aligned in a direction perpendicular to the semiconductor substrate; and
a memory element electrically connected with an end of the semiconductor pillar.
2. The dynamic random access memory device as in claim 1 , wherein the memory element is a capacitor.
3. The dynamic random access memory device as in claim 1 , wherein the bit line is electrically connected with a first end of the semiconductor pillar via the doped diffusion region and the memory element is electrically connected with a second end of the semiconductor pillar structure that is opposite the first end.
4. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar comprises an epitaxially grown semiconductor.
5. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar comprises epitaxially grown Si.
6. The dynamic random access memory device as in claim 1 , wherein the memory element is located above the surface of the semiconductor substrate such that the vertical transistor structure is between the memory element and the semiconductor substrate.
7. The dynamic random access memory device as in claim 1 , wherein the electrically conductive gate layer surrounds an outer side of the gate dielectric layer.
8. The dynamic random access memory device as in claim 1 , wherein the wordline further comprises first and second dielectric layers arranged such that the electrically conductive gate layer is located between the first and second dielectric layers.
9. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar has an end located opposite the semiconductor substrate that is doped to form a drain region.
10. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar is substantially monocrystalline.
11. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar is at least 80 percent monocrystalline by volume.
12. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar is at least 90 percent monocrystalline by volume.
13. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar comprises silicon.
14. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar comprises silicon-germanium.
15. The dynamic random access memory device as in claim 1 , wherein the semiconductor pillar comprises indium-gallium-arsenide.