Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising:

a cell unit including:

a first selection gate transistor,

a second selection gate transistor; and

a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor; and

a data write circuit configured to execute a writing operation to write data to the memory cells;

wherein

the memory cells include:

a first memory cell connected with a first word line and capable of being programmed in one stage and storing data of one bit,

a second memory cell connected with a second word line and capable of being programmed in multi-stages and storing data of three bits, the second memory cell being closer to the first selection gate transistor as compared with the first memory cell,

a third memory cell connected with a third word line and capable of being programmed in the multi-stages and storing data of three bits, the third memory cell being closer to the first selection gate transistor as compared with the second memory cell, and

a fourth memory cell connected with a fourth word line and capable of being programmed in the multi-stages and storing data of three bits; the fourth memory cell being closer to the first selection gate transistor as compared with the third memory cell; and

the data write circuit executes:

a first program on the third memory cell as a non-final stage of the multi-stages,

a second program on the fourth memory cell as a final stage of the multi-stages, after the first program,

a third program on the second memory cell as the non-final stage of the multi-stages, after the second program,

a fourth program on the third memory cell as the final stage of the multi-stages, after the third program,

a fifth program on the first memory cell as the one stage, after the fourth program, and

a sixth program on the second memory cell as the final stage of the multi-stages, after the fifth program.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein

the memory cells further include:

a fifth memory cell connected with a fifth word line and capable of being programmed in the multi-stages and storing data of three bits, the fifth memory cell being closer to the first selection gate transistor as compared with the fourth memory cell; and

the data write circuit further executes

a seventh program on the fifth memory cell as the final stage of the multi-stages, before the first program, and

an eighth program on the fourth memory cell as the non-final stage of the multi-stages, before the seventh program.

3. The nonvolatile semiconductor memory device according to claim 2 , wherein

the multi-stages includes a first stage, a second stage, and a third stage, and

the non-final stage is the second stage, and the final stage is the third stage.

4. The nonvolatile semiconductor memory device according to claim 3 , wherein

the data write circuit further executes

a ninth program on the third memory cell as the first stage of the multi-stages, before the eighth program, and

a tenth program on the second memory cell as the first stage of the multi-stages, after the seventh program and before the first program.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein

the cell unit further includes:

a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and

a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

6. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a source line connected to a source of the first selection gate transistor; and

a bit line connected to a drain of the second selection gate transistor.

7. A nonvolatile semiconductor memory device, comprising:

a cell unit including:

a first selection gate transistor,

a second selection gate transistor; and

a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor; and

a data write circuit configured to execute a writing operation to write data to the memory cells;

wherein

the memory cells include:

a first memory cell connected with a first word line and capable of being storing data of two bits,

a second memory cell connected with a second word line and capable of storing data of three bits, the second memory cell being closer to the first selection gate transistor as compared with the first memory cell,

a third memory cell connected with a third word line and capable of storing data of three bits, the third memory cell being closer to the first selection gate transistor as compared with the second memory cell,

a fourth memory cell connected with a fourth word line and capable of storing data of three bits, the fourth memory cell being closer to the first selection gate transistor as compared with the third memory cell, and

a fifth memory cell connected with a fifth word line and capable of storing data of three bits, the fifth memory cell being closer to the first selection gate transistor as compared with the fourth memory cell; and

the data write circuit executes:

a first program on the fourth memory cell as a non-final one of stages for writing three bits,

a second program on the fifth memory cell as a final one of stages for writing three bits, after the first program,

a third program on the third memory cell as the non-final one stages for writing three bits, after the second program,

a fourth program on the fourth memory cell as the final one of stages for writing three bits, after the third program,

a fifth program on the second memory cell as the non-final one of stages for writing three bits, after the fourth program,

a sixth program on the first memory cell as a final one of stages for writing two bits, after the fifth program, and

a seventh program on the second memory cell as the final one of stages for writing three bits, after the sixth program.

8. The nonvolatile semiconductor memory device according to claim 7 , wherein

the data write circuit further executes

an eighth program on the first memory cell as a non-final one of stages for writing two bits, after the fourth program and before the fifth program.

9. The nonvolatile semiconductor memory device according to claim 8 , wherein

the three bits are written in first to third stages, among which the third stage corresponds to the final one, and the second stage corresponds to the non-final one, and

the two bits are written in first and second stages, among which the second stage corresponds to the final one, and the first stage corresponds to the non-final one.

10. The nonvolatile semiconductor memory device according to claim 9 , wherein

the data write circuit further executes

a ninth program on the third memory cell as the first stage for writing three bits, before the first program, and

a tenth program on the second memory cell as the first stage for writing three bits, after the second program before the third program.

11. The nonvolatile semiconductor memory device according to claim 7 , wherein

the cell unit further includes:

a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and

a second dummy cell having a structure same as one of the memory cells between the first selection rate transistor and the fifth memory cell.

12. The nonvolatile semiconductor memory device according to claim 7 , further comprising:

a source line connected to a source of the first selection gate transistor; and

a bit line connected to a drain of the second selection gate transistor.