IP Library › Granted Patent US 11,088,542
Granted Patent B1
US 11,088,542 · App. 16/777,195 · Granted Aug 10, 2021

System and method for temperature compensated ESD protection

Inventors: Gernot Langguth (Oberhaching, DE); Adrien Benoit Ille (Unterhaching, DE); Steffen Schumann (Munich, DE)
Assignee: INFINEON TECHNOLOGIES AG
H02H9/046H01L27/0255H01L27/0285H01L27/0288H02H9/005
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Quick Facts
Patent No.
US 11,088,542
App. No.
16/777,195
Granted
Aug 10, 2021
Kind
B1
Abstract

In accordance with an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.

Claims (47)

1. A method for electrostatic discharge (ESD) protection, the method comprising:

dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage;

compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage;

monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and

activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.

2. The method of claim 1 , further comprising amplifying the temperature compensated divided voltage and providing the amplified temperature compensated divided voltage to an input node of the clamp circuit.

3. The method of claim 2 , further comprising amplifying the transient detection signal and providing the amplified transient detection signal to the clamp circuit.

4. The method of claim 2 , further comprising providing the transient detection signal to the voltage divider circuit.

5. The method of claim 2 , further comprising amplifying the transient detection signal, and providing the amplified transient detection signal to the voltage divider circuit.

6. The method of claim 1 , wherein temperature compensating the voltage divider circuit comprises providing a temperature dependent current to a node of the voltage divider circuit.

7. The method of claim 1 , wherein the voltage divider circuit comprises a plurality of diode circuits coupled in series with a resistor.

8. The method of claim 7 , wherein:

each diode circuit of the plurality of diode circuits comprises a diode connected transistor; and

temperature compensating the voltage divider circuit comprises using a temperature compensation circuit comprising a transistor having a load path coupled between a node of the voltage divider circuit and one of the plurality of circuit nodes, and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor.

9. The method of claim 1 , wherein the transient detection circuit comprises an RC circuit.

10. An electrostatic discharge (ESD) circuit comprising:

a voltage divider circuit coupled between a first circuit node and a second circuit node;

a temperature compensation circuit coupled to the voltage divider circuit;

a transient detection circuit coupled to at least one of the first circuit node or the second circuit node; and

a clamp circuit having a load path coupled between the first circuit node and the second circuit node, and a control node coupled to an output of the voltage divider circuit and to an output of the transient detection circuit.

11. The ESD circuit of claim 10 , further comprising a first amplifier coupled between the output of the voltage divider circuit and the control node of the clamp circuit.

12. The ESD circuit of claim 11 , further comprising a second amplifier coupled between the output of the transient detection circuit and the control node of the clamp circuit.

13. The ESD circuit of claim 11 , further comprising a second amplifier coupled between the output of the transient detection circuit and the voltage divider circuit.

14. The ESD circuit of claim 11 , wherein the first amplifier comprises an inverter.

15. The ESD circuit of claim 10 , wherein:

the voltage divider circuit comprises a plurality of diode circuits coupled in series with a resistor; and

the temperature compensation circuit is configured to provide a temperature dependent current.

16. The ESD circuit of claim 15 , wherein:

each of the plurality of diode circuits comprises a diode connected transistor; and

the temperature compensation circuit comprises a transistor having a load path coupled between a node of the voltage divider circuit and one of first circuit node or the second circuit node, and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor.

17. The ESD circuit of claim 15 , wherein the temperature compensation circuit comprises a plurality of temperature compensation circuits.

18. The ESD circuit of claim 10 , wherein the first circuit node is a power supply node, and the second circuit node is a ground node.

19. The ESD circuit of claim 10 , wherein the transient detection circuit comprises an RC circuit coupled to at least one of the first circuit node or the second circuit node.

20. An integrated circuit comprising:

a plurality of diode connected transistors and at least one resistor disposed on a semiconductor substrate, the plurality of diode connected transistors and the at least one resistor coupled in series between a first power supply connection and a second power supply connection;

a temperature compensation circuit disposed on the semiconductor substrate, the temperature compensation circuit coupled to the plurality of diode connected transistors and the at least one resistor;

a filter resistor and a filter capacitor disposed on the semiconductor substrate, the filter resistor and the filter capacitor coupled in series between the first power supply connection and the second power supply connection;

a clamping transistor disposed on the semiconductor substrate, the clamping transistor having a load path connected between the first power supply connection and the second power supply connection;

a first amplifier disposed on the semiconductor substrate, the first amplifier coupled between the plurality of diode connected transistors and a control node of the clamping transistor; and

a second amplifier disposed on the semiconductor substrate, the second amplifier coupled between the filter capacitor and the control node of the clamping transistor.

21. The integrated circuit of claim 20 , wherein:

each of the plurality of diode connected transistors comprises a diode connected MOS transistor; and

the clamping transistor comprises a MOS transistor.

22. The integrated circuit of claim 21 , wherein: the temperature compensation circuit comprises:

a first MOS transistor having a first source/drain coupled to the plurality of diode connected transistors and a second source/drain coupled to the second power supply connection;

a first resistor coupled between a gate of the first MOS transistor and the first source/drain; and

a second resistor coupled between the gate and the second source/drain.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2020
From: LANGGUTH, GERNOT; ILLE, ADRIEN BENOIT; SCHUMANN, STEFFEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 051674/0525 →
Cited By (2)
US 12,537,375 US 12,573,843