IP Library › Granted Patent US 11,281,607
Granted Patent B2
US 11,281,607 · App. 16/777,366 · Granted Mar 22, 2022

Paravirtualized cluster mode for legacy APICs

Inventor: Bandan Das (Westford, MA)
Assignee: RED HAT, INC.
G06F13/24G06F9/45558G06F2009/45579
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Quick Facts
Patent No.
US 11,281,607
App. No.
16/777,366
Granted
Mar 22, 2022
Kind
B2
Abstract

According to one example, a method includes, with a hypervisor, advertising a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight. The method further includes, associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2 N different values. The method further includes, with the hypervisor, in response to receiving an interrupt for the virtual machine, determining to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.

Claims (32)

1. A method comprising:

with a hypervisor, advertising a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight, the logical destination mode allowing for designation of a group of the plurality of virtual cores as a delivery destination for an interrupt;

associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2 N different values; and

with the hypervisor, in response to receiving an interrupt for the virtual machine, determining to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.

2. The method of claim 1 , wherein the hypervisor advertises the paravirtualized cluster mode via a Central Processing Unit Identifier (CPUID) bit.

3. The method of claim 2 , further comprising, with the guest, checking for support of the paravirtualized cluster mode by using a CPUID instruction.

4. The method of claim 1 , further comprising, with the guest, enabling the paravirtualized cluster mode by writing zeros to bits 28 - 31 of a destination format register.

5. The method of claim 1 , where N equals eight.

6. The method of claim 1 , wherein the N-bit identifier is represented by bits 24 - 31 of a logical destination register.

7. The method of claim 1 , wherein the destination address is a 32-bit address and the subset of bits is eight bits.

8. The method of claim 7 , wherein the destination address specifies up to four different possible destinations for the interrupt.

9. The method of claim 7 , wherein to send the interrupt to more than four different possible destinations, the guest sets two logical destination registers associated with two different virtual cores of the plurality of virtual cores to have a same value.

10. A method comprising:

with a guest using a legacy Advanced Programmable Interrupt Controller (APIC), determining that a hypervisor supports a paravirtualized cluster mode, the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight, the logical destination mode allowing for designation of a group of the plurality of virtual cores as a delivery destination for an interrupt;

with the guest, enabling the paravirtualized cluster mode;

associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2 N different values; and

with the guest, setting N bits in a logical destination register to indicate the N-bit identifier associated with a virtual core of the plurality of virtual cores.

11. The method of claim 10 , wherein enabling the paravirtualized cluster mode comprises writing zeros to bits 28 - 31 of a destination format register.

12. The method of claim 10 , wherein determining whether the hypervisor supports the paravirtualized cluster mode comprises the guest checking a Central Processing Unit Identifier (CPUID) instruction.

13. The method of claim 10 , where N equals eight.

14. The method of claim 10 , wherein the N-bit identifier is represented by bits 24 - 31 of the logical destination register.

15. The method of claim 10 , further comprising, with the guest, processing an interrupt with a destination address, wherein the destination address is a 32-bit address.

16. The method of claim 15 , wherein the destination address specifies up to four different possible destinations for the interrupt.

17. The method of claim 15 , wherein to send the interrupt to more than four different possible destinations, the guest sets N bits in two logical destination registers associated with two different virtual cores of the plurality of virtual cores to have a same N-bit identifier.

18. A computing system comprising:

a processor; and

a memory comprising machine readable instructions that when executed by the processor, cause the system to:

advertise a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight, the logical destination mode allowing for designation of a group of the plurality of virtual cores as a delivery destination for an interrupt;

associate each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2N different values; and

in response to receiving an interrupt for the virtual machine, determine to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.

19. The system of claim 18 , wherein a hypervisor advertises the paravirtualized cluster mode via a Central Processing Unit Identifier (CPUID) bit.

20. The system of claim 18 , wherein the destination address is a 32-bit address and the subset of bits is eight bits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2020
From: DAS, BANDAN
To: RED HAT, INC.
Reel/Frame 051686/0575 →
Continuity (1)
Related Publication 20210240644A1 · Aug 5, 2021
Cited By (1)
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